1: 2: 3: 4: NCO Clock Reference (CLKR) Interrupt-on-Change Basic CCP1 CCP2 CCP3 CCP4 CCP5 PWM6OUT PWM7OUT CLC TMR0 CCP and PWM DSM CWG TX/ CK(3) DT(3) Timers/SMT SDO1 SCK1 SDO2 SCK2 EUSART — DSM C1OUT C2OUT MSSP (SPI/I2C™) — Zero-Cross Detect — CWG1A CWG1B CWG1C CWG1D CWG2A CWG2B CWG2C CWG2D CWG3A CWG3B CWG3C CWG3D CLC1OUT CLC2OUT CLC3OUT CLC4OUT NCO CLKR — — This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 5 for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 6. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C™ logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. DS40001768A-page 9 PIC16(L)F1885X/7X Advance Information Note ADGRDA ADGRDB Comparators — DAC — Voltage Reference 28-Pin (U)QFN OUT(2) ADC 28-Pin SPDIP/SOIC/SSOP 28-PIN ALLOCATION TABLE (PIC16(L)F1885X) I/O 2014 Microchip Technology Inc. TABLE 3:
