Product Brief PIC18FXXQ84 (Microchip)

PIC18FXXQ84 PIC18FXXQ84 Family Product Brief Introduction
The PIC18 Q84 microcontroller family is available in 28/40/44/48-pin devices for many automotive and industrial applications. The many communication peripherals found on the product family, such as CAN, SPI, I2C, two UARTs, can handle a wide range of wired and wireless (using external modules) communication protocols for intelligent applications. This, combined with the Core Independent Peripherals integration capabilities, enable functions for motor control, power supply, sensor, signal and user interface applications. Additionally, this family includes a 12-bit ADC with Computation and context saving (ADC3) extensions for automated signal analysis to reduce the complexity of the application.
PIC18 Q84 Family Types Table 1. Devices Included in This Data Sheet T/ imer imer imer aveform imers 2 C 3 (channels) oltage Detect atchdog T Device CCP (bytes) (bytes) (bytes) I/O Pins/ imer with HL CAN FD SPI/I UART/ Data SRAM Generator Oscillator 8-Bit DAC Data EEPROM 16-Bit T Comparator/ 16-Bit Dual PWM/ Zero-Cross Detect ectored Interrupts Peripheral Pin Select 8-Bit T V Program Memory Flash 16-Bit Universal T Numerically Controlled Temperature Indicator Memory Access Partition/ Device Information Area Configurable Logic Cell 12-Bit ADC indowed W Complimentary W Signal Measurement T High-Low V 32-Bit CRC with Scanner UART with Protocol Support Peripheral Module Disable Direct Memory Access (DMA) W
PIC18F26Q84 64k 4096 1024 Y/Y 25/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F27Q84 128k 8192 1024 Y/Y 25/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F46Q84 64k 4096 1024 Y/Y 36/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F47Q84 128k 8192 1024 Y/Y 36/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F56Q84 64k 4096 1024 Y/Y 44/Y 3/3 4/3 3 1 2 3 8 35 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F57Q84 128k 8192 1024 Y/Y 44/Y 3/3 4/3 3 1 2 3 8 35 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y
Features
• C Compiler Optimized RISC Architecture • Operating Speed: – DC – 64 MHz clock input – 62.5 ns minimum instruction cycle • Eight Direct Memory Access (DMA) Controllers: – Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces – User programmable source and destination sizes – Hardware and software triggered data transfers • Vectored Interrupt Capability: – Selectable high/low priority – Fixed interrupt latency of three instruction cycles – Programmable vector table base address © 2019 Microchip Technology Inc.
Product Brief
DS40002148A-page 1 Document Outline Introduction PIC18 Q84 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Table of Contents 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service