Datasheet PIC18(L)F2X/4X/5XK42 (Microchip) - 14

DS4
PIC18(L)F2X/4X/5XK4
0001861B-p
TABLE 5: 48-PIN ALLOCATION TABLE FOR PIC18(L)F5XK42 e KR) L ge
age 14
c n N n tect T C a FP F rs re e ( e h Q Q D M fe to c C /S PWM O U e ra O n ss C M d C n- I/ n T a in 2 rs n ADC p I SPI re asic e R DAC ro UART DS e CWG CL NC t-o B -Pi P m fe 8 C m up 4 ag 48- lt Co ro Ti Re rr o e CCP a k V Z c te In Clo
RA0 21 21 ANA0 — — C1IN0- — — — — — — — — CLCIN0
(1)
— — IOCA0 — C2IN0- RA1 22 22 ANA1 — — C1IN1- — — — — — — — — CLCIN1
(1)
— — IOCA1 — C2IN1-
A
RA2 23 23 ANA2 VREF- DAC1OUT1 C1IN0+ — — — — — — — — — — — IOCA2 —
d
C2IN0+
va
RA3 24 24 ANA3 VREF+ — C1IN1+ — — — — MDCARL
(1)
- — — — — — IOCA3 —
nce Inf
RA4 25 25 ANA4 — — — — — — — MDCARH
(1)
T0CKI
(1)
— — — — — IOCA4 — RA5 26 26 ANA5 — — — — — SS1
(1)
— MDSRC
(1)
— — — — — — IOCA5 — RA6 33 33 ANA6 — — — — — — — — — — — — — — IOCA6 OSC2
2
CLKOUT
o
RA7 32 32 ANA7 — — — — — — — — — — — — — — IOCA7 OSC1
rm
CLKIN
at
RB0 8 8 ANB0 — — C2IN1+ ZCD — — — — — CCP4
(1)
CWG1IN
(1)
— — — INT0
(1)
— IOCB0
ion
RB1 9 9 ANB1 — — C1IN3- — SCL2
(3,4)
— — — — — CWG2IN
(1)
— — — INT1
(1)
— C2IN3- IOCB1 RB2 10 10 ANB2 — — — — SDA2
(3,4)
— — — — — CWG3IN
(1)
— — — INT2
(1)
— IOCB2 RB3 11 11 ANB3 — — C1IN2- — — — — — — — — — — — IOCB3 — C2IN2- RB4 16 16 ANB4 — — — — — — — — T5G
(1)
— — — — — IOCB4 — ADCACT
(1)
 RB5 17 17 ANB5 — — — — — — — — T1G
(1)
CCP3
(1)
- — — — IOCB5 — 20 RB6 18 18 ANB6 — — — — — — CTS2
(1)
— — — — CLCIN2
(1)
— — IOCB6 ICSPCLK 16 M RB7 19 19 ANB7 — DAC1OUT2 — — — — RX2
(1)
— T6IN
(1)
— — CLCIN3
(1)
— — IOCB7 ICSPDAT ic RC0 34 34 ANC0 — — — — — — — — T1CKI
(1)
— — — — — IOCC0 SOSCO rochip T3CKI
(1)
T3G
(1)
SMTWIN1
(1)
T e RC1 35 35 ANC1 — - — — — — — — SMTSIG1
(1)
CCP2
(1)
— — — — IOCC1 SOSCI c hnology
Note 1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2:
All output signals shown in this row are PPS remappable.
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4:
These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will In be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. c . Document Outline Description Core Features Memory Operating Characteristics Power-Saving Functionality eXtreme Low-Power (XLP) Features Digital Peripherals Digital Peripherals (Continued) Analog Peripherals Flexible Oscillator Structure TABLE 1: PIC18(L)F2X/4X/5XK42 Family Types TABLE 2: Packages FIGURE 1: 28-Pin SPDIP, SOIC, SSOP for PIC18(L)F2XK42 FIGURE 2: 28-Pin UQFN (4x4) for PIC18(L)F2XK42 FIGURE 3: 28-Pin QFN (6x6x0.9 mm) for PIC18(L)F2XK42 FIGURE 4: 40-Pin PDIP for PIC18(L)F4XK42 FIGURE 5: 40-Pin UQFN (5x5x0.5 mm) for PIC18(L)F4XK42 FIGURE 6: 44-Pin QFN (8x8x0.9 mm) for PIC18(L)F5XK42 FIGURE 7: 44-Pin TQFP For PIC18(L)F4XK42 FIGURE 8: 48-Pin TQFP/UQFN for PIC18(L)F5XK42 TABLE 3: 28-Pin Allocation Table (PIC18(L)F2XK42) TABLE 4: 40/44-Pin Allocation Table For PIC18(L)F4XK42, PIC18(L)F5XK42 TABLE 5: 48-Pin Allocation Table for PIC18(L)F5XK42 Trademarks Worldwide Sales