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Datasheet 6N138, 6N139 (Toshiba) - 4

ПроизводительToshiba
ОписаниеPhotocoupler IRED & Photo IC
Страниц / Страница6 / 4 — Switching Specifications (Ta=25°C, VCC=5V, unless otherwise specified)
Формат / Размер файлаPDF / 308 Кб
Язык документаанглийский

Switching Specifications (Ta=25°C, VCC=5V, unless otherwise specified)

Switching Specifications (Ta=25°C, VCC=5V, unless otherwise specified)

16 предложений от 15 поставщиков
Быстродействующие оптопары Darlington 100KBd Transistor Output
6N139(F)
Toshiba
16 ₽
Десси
Россия
Диод 1SMB24CA
ON Semiconductor
21 ₽
Romstore
Россия, Беларусь
HSMS-2820-BLKG
от 125 ₽
6N139S-TA1
Lite-On
по запросу
Выбираем схему BMS для заряда литий-железофосфатных (LiFePO4) аккумуляторов

Модельный ряд для этого даташита

Текстовая версия документа

6N138,6N139
Switching Specifications (Ta=25°C, VCC=5V, unless otherwise specified)
Test Characteristics Symbol Test Condition Min Typ. Max Unit Circuit IF = 0.5 mA, RL = 4.7 kΩ  5 25 Propagation delay 6N139 time to logic low tpHL(*) 1 IF = 12 mA, RL = 270 Ω  0.2 1 µs at output (Note 6, 8) 6N138 IF = 1.6 mA, RL = 2.2 kΩ  1 10 IF = 0.5 mA, RL = 4.7 kΩ  5 60 Propagation delay 6N139 time to logic high tpLH(*) 1 IF = 12 mA, RL = 270 Ω  1 7 µs at output (Note 6, 8) 6N138 IF = 1.6 mA, RL = 2.2 kΩ  4 35 Common mode transient I immunity at logic high CM F = 0 mA, RL = 2.2 kΩ H 2  500  V / µs V level output (Note 9) CM = 400 Vp−p Common mode transient IF =1.6 mA immunity at logic low CML 2 RL = 2.2 kΩ  −500  V / µs level output (Note 9) VCM = 400 Vp−p (*)JEDEC registered data. (Note 1): Derate linearly above 50 °C free−air temperature at a rate of 0.4 mA / °C (Note 2): Derate linearly above 50 °C free−air temperature at a rate of 0.7 mW / °C (Note 3): Derate linearly above 25 °C free−air temperature at a rate of 0.7 mA / °C (Note 4): Derate linearly above 25 °C free−air temperature at a rate of 2.0 mW / °C (Note 5): DC CURRENT TRANSFER RATIO is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100 %. (Note 6): Pin 7 open. (Note 7): Device considered a two−terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7 and 8 shorted together. (Note 8): Use of a resistor between pin 5 and 7 will decrease gain and delay time. (Note 9): Common mode transient immunity in logic high level is the maximum tolerable (positive) dVCM / dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a logic high state (i.e. VO > 2.0 V). Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dVCM / dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e. VO < 0.8 V). © 2019 4 2019-06-10 Toshiba Electronic Devices & Storage Corporation
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