Product Brief[AK8464] TG Phase Resolution: 56 phases Maximum Pixel Rate: 35 MHz TG Output pin: 12 pins (TG0-11 pins) For CCD Pixel clock resolution pulse: Shift pulse: <SH0> ~ <SH6> Phase Adjustable clock: <P0>, <P1>, <P2>, <PRS>, <PCL> For CIS Pixel clock resolution pulse: <SP1>, <SP2>, <LED0> ~ <LED5>, <LED_EN> Phase Adjustable clock: <CISCK> LVDS Output Format: 5 Data Pairs, 1 clock pair (channel Link) CPU I/F: 4-wire Serial Interface Power Supply 3.0V-3.6V Single Power Consumption: 696mW (typ.) Operation Temperature: 0 ~ 85 ºC Package: 56-pin QFN (With TAB exposure, 0.4mm pitch, 7mm□) Rev.1.00E 2019/6 - 2 -
