Datasheet SiC476, SiC477, SiC478, SiC479 (Vishay) - 2

SiC476, SiC477, SiC478, SiC479
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PIN CONFIGURATION
ND W ND DD G FB OUT OUT FB G W DD MODE V I LIM f S A V V V V A f S I LIM V 27 26 25 24 23 22 21 NC 20 20 21 NC 22 23 24 25 26 27 MODE V IJ CIN 1 19 SS SS 19 1 V CIN PGOOD 2 28 AGND 18 NC NC 18 28 A GND 2 P GOOD 17 P P 17 GND GND EN 3 3 EN 16 V V 16 DRV DRV BOOT 4 15 GL GL 15 4 BOOT 30 14 SW SW 14 PHASE 5 VIN 29 29 PGND 13 SW 30 P V 5 PHASE SW 13 IN GND PHASE 6 ķ ķ 6 PHASE 12 SW SW 12 7 8 9 9 8 7 10 11 11 10 IN ND IN IN IN V ND ND ND ND ND G V V V G G G G G P P P P P P
Fig. 3 - Pin Configuration PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION
Supply voltage for internal regulators V 1 V DD and VDRV. This pin should be tied to VIN, but can also be CIN connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators Open-drain power good indicator - high impedance indicates power is good. An external pull-up 2 PGOOD resistor is required Enable pin. Tie high / low to enable / disable the IC accordingly. This is a high voltage compatible pin, 3 EN can be tied to 55 V 4 BOOT High side driver bootstrap voltage 5, 6 PHASE Return path of high side gate driver 7, 8, 29 VIN Power stage input voltage. Drain of high side MOSFET 9, 10, 11, 17, 30 PGND Power ground 12, 13, 14 SW Power stage switch node 15 GL Low side MOSFET gate signal Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, V 16 V DRV is DRV the LDO output. Connect a 4.7 μF decoupling capacitor to PGND 18, 21 NC No connection internally Set the soft start ramp by connecting a capacitor to A 19 SS GND. An internal current source will charge the capacitor 20 VOUT Output voltage sense point for internal ripple injection components Feedback input for switching regulator used to program the output voltage - connect to an external 22 VFB resistor divider from VOUT to AGND 23, 28 AGND Analog ground 24 fSW Set the on-time by connecting a resistor to AGND 25 ILIMIT Set the current limit by connecting ILIMIT pin to AGND, float or VDD 26 VDD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND 27 Mode Set various operation modes by connecting a resistor to AGND. See specification table for details S19-0910-Rev. C, 28-Oct-2019
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