SiC466, SiC467, SiC468, SiC469 www.vishay.com Vishay Siliconix Power Good SiC46x’s power good is an open-drain output. Pull PGOOD pin high up to 5 V through a 10K resistor to use this signal. Power good window is shown in the Fig. 8. If voltage level VFB_Rising_Vth_OV (typ. = 0.96 V) VFB_Falling_Vth_OV on FB pin is out of this window, PG signal is de-asserted by (typ. = 0.91 V) pulling down to GND. To prevent false triggering during Vref (0.8 V) transient events, P VFB_Falling_Vth_UV GOOD has a 25 μs blanking time. V (typ. = 0.72 V) VFB_Rising_Vth_UV FB (typ. = 0.77 V) Pull-high PG Pull-low Fig. 8 - PGOOD Window and Timing DiagramSiC46x microBUCK FAMILY SCHEMATIC EN R_EN_H R_EN_L Heading 560K DNP t o 3 o 3. t NC PG b o F o μ R_ R_PGD _b 1 Notes in small C 0. 102K Css 33nF black text near 3 component EN 6 5 4 18 2 19 Rmode values refer to E2 E1 SS Mode 27 Vishay SiC46x S S NC 1 spreadsheet VCIN A A OOT OOD 2K B Cdd G 29 calcualtor VIN-PAD 26 PH PH P VDD references 7 VIN1 1μF +Vin 8 25 ILIMIT VIN2 6V to 60V Cin_D R_fsw 0.1μF 28 AGND-PAD SiC466 FSW 24 30 PGND-PAD 52.3K SiC467 9 23 AGND PGND1 SiC468 10 PGND2 R_FB_L SiC469 VFB 22 11 PGND3 10K Cin 17 PGND 21 NC V 47μF R T L W1 W2 W3 OU G VD S S S V AGND 15 16 12 13 14 20 R_FB_H 52.3K Analog ground +VOUT = 5 V (A ), and power GND Cdrv ground (P ) L 0.1μF 64 μF 64 μF GND are tied internally 4.7μF Cout_D Cout_C Cout_B in the SiC46x PGND Fig. 9 - SiC467 Configured for 6 V to 60 V Input, 5 V Output at 6 A, 500 kHz Operation with Power Save Mode Enabledall Ceramic Output Capacitance Design S19-0911-Rev. E, 28-Oct-2019 9 Document Number: 76044 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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