link to page 2 link to page 2 link to page 2 48L512/48LM01General DescriptionPowering the Device During SRAM to EEPROM Backup (V The Microchip Technology Inc. 48L512/48LM01 CAP) (48LXXX) serial EERAM has an SRAM memory core A small capacitor (typically 47 μF to 100 μF) is required with hidden EEPROM backup. The device can be for the proper operation of the device. This capacitor is treated by the user as a full symmetrical read/write placed between VCAP (pin 3) and the system VSS (see SRAM. Backup to EEPROM is handled by the device Normal Device Operation). When power is first applied on any power disrupt, so the user can effectively view to the device, this capacitor is charged to VCC through this device as an SRAM that never loses its data. the device (see Normal Device Operation). During nor- The device is structured as a 512/1024-Kbit SRAM mal SRAM operation, the capacitor remains charged to with EEPROM backup in each memory cell. The VCC and the level of system VCC is monitored by the SRAM is organized as 65,536 x 8 bits or device. If system VCC drops below a set threshold, the 131,072 x 8 bits, and uses the SPI serial interface. device interprets this as a power-off or brown-out The SPI bus uses three signal lines for event. The device suspends all I/O operation, shuts off communication: clock input (SCK), data in (SI), and its connection with the VCC pin, and uses the saved data out (SO). Access to the device is controlled energy in the capacitor to power the device through the through a Chip Select (CS) input, allowing any number VCAP pin as it transfers all SRAM data to EEPROM of devices to share the same bus. (see Vcc Power-Off Event). On the next power-up of VCC, the data is transfered back to SRAM, the capaci- The SRAM is a conventional serial SRAM: it allows tor is recharged, and the SRAM operation continues. symmetrical reads and writes and has no limits on cel usage. The backup EEPROM is invisible to the user Normal Device Operation and cannot be accessed by the user independently. The device includes circuitry that detects VCC V (pin 8) System V dropping below a certain threshold, shuts its CC CC connection to the outside environment, and transfers V Monitor CC all SRAM data to the EEPROM portion of each cell for V (pin 3) CAP safe keeping. When VCC returns, the circuitry automatically returns the data to the SRAM and the C Charged to V VCAP CC user’s interaction with the SRAM can continue with the CS Normal SO same data set. SRAM SI Operation V (pin 4) SS SCK Block Diagram HOLD System VSS VCC Power Control VCAP Block VCC Power-Off Event Memory Address and Data Control V (pin 8) System V CS CC CC SPI Control Logic Automatic Logic SO Backup SI and Address V (pin 3) Decoder CAP SCK HOLD EEPROM C Temporary V SRAM VCAP CC EEPROM 128K x 8 CS STATUS 64K x 8 SO SRAM to Register SI V (pin 4) EEPROM SS SCK SRAM Transfer 128K x 8 HOLD STORE System V 64K x 8 SS RECALL 2018-2019 Microchip Technology Inc. DS20006008C-page 2 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L512/48LM01 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Byte Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L512/48LM01 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow FIGURE 11-4: AutoStore/AutoRecall Scenarios (with ASE = 0, Array Modified) FIGURE 11-5: AutoStore/AutoRecall Scenarios (with ASE = 1 or Array Not Modified) 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales
