AD22057APPLICATION HINTS network helps to absorb the additional charge, effectively lower- Frequency Compensation ing the high frequency output impedance of the AD22057. For As are all closed-loop op amp circuits, the AD22057 is sensitive these applications the output signal should be taken from the to capacitive loading at its output. However, the AD22057 is midpoint of the RLAG–CLAG combination as shown in Figure 15. sensitive at higher output voltages due to nonlinear effects in Since the perturbations from the analog-to-digital converter are the rail-to-rail design of the buffer amplifier (A2). In this small, the output of the AD22057 will appear to be a low amplifier the output stage gain increases with increasing output impedance. The transient response will, therefore, have a voltage. This behavior does not affect dc parameters such as time constant governed by the product of the two lag compo- gain accuracy or linearity; however, it can compromise ac sta- nents, CLAG × RLAG. For the values shown in Figure 15, this bility. When operating from a power supply of 5 V or less (and, time constant is programmed at approximately 10 µs. There- therefore, VOUT < 5 V), the AD22057 can drive capacitive fore, if samples are taken at several tens of microseconds or more, loads up to 25 pF with no external components. When operat- there will be negligible “stacking up” of the charge injections. ing at higher supply voltages (which are associated with higher output voltages) and/or driving larger capacitive loads, an exter- +VS nal compensation network should be used. Figure 14 shows an AD22057 R-C “snubber” circuit loading the output of the AD22057. LOADA2 This combination, in conjunction with the internal 20 kΩ resis- tance, forms a lag network. This network attenuates the open- 10k V RLAGRLCL loop gain of the amplifier at higher frequencies. The ratio of R CLAG LAG to the load seen by the AD22057 determines the high frequency attenuation seen by the op amp. If R 10k V LAG is made 1/20th of the total load resistance (≈20 kΩ储RL), then 26 dB of attenuation is obtained at higher frequencies. The capacitor (CLAG) is used to control the frequency of the compensation Figure 14. Using an R-C Network for Compensation network. It should be set to form a 5 µs time constant with the +VS resistor (RLAG). Table I shows the recommended values of RLAG and CLAG for various values of external load resistor RL. AD22057 Ten percent tolerance on these components is acceptable. A21k V Alternatively, the signal may be taken from the midpoint of IN R 0.01 m F m PROCESSOR LAG–CLAG. This output is particularly useful when driving 10k V A/D CMOS analog-to-digital converters. For more information see the section Driving Charged Redistributed A/D Converters. 10k V Note that when implementing this network large signal re- sponse is compromised. This occurs because there is no active pull-down and the lag capacitor must discharge through the Figure 15. Recommended Circuit for Driving CMOS A/D internal feedback resistor (20 kΩ) giving a fairly long-time Converters constant. For example if CLAG = 0.01 µF, the large signal negative slew characteristic is a decaying exponential with a UNDERSTANDING THE AD22057 time constant of ≈200 µs. Figure 16 shows the main elements of the AD22057. The signal inputs at Pins 1 and 8 are first applied to dual resistive attenua- Table I. Compensation Components vs. External Load tors R1 through R4, whose purpose is to reduce the common- Resistor mode voltage at the input to the preamplifier. The attenuated R signal is then applied to a feedback amplifier based on the very LRLAGCLAG low drift op amp, A1. The differential voltage across the inputs >100 kΩ 470 Ω 0.01 µF is accurately amplified in the presence of common-mode volt- > 50 kΩ 390 Ω 0.01 µF ages of many times the supply voltage. The overall common- > 20 kΩ 270 Ω 0.047 µF mode response is minimized by precise laser trimming of R3 > 10 kΩ 200 Ω 0.047 µF and R4, giving the AD22057 a common-mode rejection ratio > 5 kΩ 100 Ω 0.1 µF (CMRR) of at least 80 dB (10,000:1). > 2 kΩ 47 Ω 0.22 µF The common-mode range of A1 extends from slightly below Driving Charge Redistribution A/D Converters ground to 1 V below +VS (at the minimum temperature of When driving CMOS ADCs, such as those embedded in popu- –40°C). Since an attenuation ratio of about 6 is used, the input lar microcontrollers, the charge injection (∆Q) can cause a common-mode range is –1 V to +24 V using a +5 V supply. significant deflection in the AD22057 output voltage. Though Small filter capacitors C1 and C2 are included to minimize the generally of short duration, this deflection may persist until effects of spurious RF signals at the inputs, which might cause after the sample period of the ADC has expired. It is due to the dc errors due to the rectification effects at the input to A1. At relatively high open-loop output impedance of the AD22057. high frequencies, even a small imbalance in these components The effect can be significantly reduced by including the same would seriously degrade the CMRR, so a special high frequency R-C network recommended for improving stability (see Fre- trim is also carried out during manufacture. quency Compensation section). The large capacitor in the lag REV. B –7–
