Datasheet PT7C4363BQ (Diodes) - 7

PT7C4363BQ Over the Operating Range Symbol Item Min. Typ. Max. Unit
fSCL SCL clock frequency - - 400 kHz tSU;STA START condition set-up time 0.6 - - µs tHD;STA START condition hold time 0.6 - - µs tSU;DAT Data set-up time (RTC read/write) 200 - - ns tHD;DAT1 Data hold time (RTC write) 35 - - ns tHD;DAT2 Data hold time (RTC read) 0 - - µs tSU;STO STOP condition setup time 0.6 - - µs tBUF Bus idle time between a START and STOP condition 1.3 - - µs tLOW When SCL = "L" 1.3 - - µs tHIGH When SCL = "H" 0.6 - - µs tr Rise time for SCL and SDA - - 0.3 µs tf Fall time for SCL and SDA - - 0.3 µs tSP* Allowable spike time on bus - - 50 ns CB Capacitance load for each bus line - - 400 pF
* Note:
Only reference for design. S Sr P tSU;STA SCL t t LOW HIGH tHD;STA tSP fSCL tBUF SDA t t t t t t HD;STA SU;DAT HD;DAT SU;STA SU;STO HD;STA S Start condition P Stop condition Sr Restart condition PT7C4363BQ
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July 2019 Document Number DS42042 Rev 1-2 7 © Diodes Incorporated Document Outline Features Description Pin Configuration Pin Description Function Block Maximum Ratings Recommended Operating Conditions DC Electrical Characteristics AC Electrical Characteristics Recommended Layout for Crystal Cpar is all parasitical capacitor between X1 and X2. Crystal Specifications Function Description Overview of Functions Registers Control and Status Register Time Counter Days of the Week Counter Calendar Counter AE W4 Communication I2C Bus Interface Overview of I2C-BUS System Configuration Starting and Stopping I2C Bus Communications Slave Address Part Marking Mechanical Information