link to page 31 link to page 32 link to page 32 link to page 33 link to page 33 link to page 34 link to page 34 link to page 34 link to page 34 link to page 35 link to page 36 link to page 36 link to page 37 link to page 37 link to page 48 link to page 49 link to page 51 link to page 51 link to page 52 link to page 52 link to page 53 link to page 53 link to page 54 link to page 55 link to page 55 link to page 56 link to page 56 link to page 57 link to page 57 link to page 58 link to page 58 link to page 59 link to page 60 link to page 61 link to page 62 Ultra-Low Power Voice Codec CMX655D Figure 36 SPI Read Transfer ... 31 Figure 37 SPI N-Byte Write Transfer .. 32 Figure 38 SPI N-Byte Read Transfer ... 32 Figure 39 TWI Write Transfer .. 33 Figure 40 TWI Read Transfer Address Phase ... 33 Figure 41 TWI Read Transfer Data Phase... 34 Figure 42 TWI Interrupt Status Register Read Transfer ... 34 Figure 43 TWI N-Byte Write Transfer .. 34 Figure 44 TWI N-Byte Read Transfer.. 34 Figure 45 I2S Mode Data Transfer ... 35 Figure 46 Left-Justified Mode Data Transfer ... 36 Figure 47 PCM Mode Dual-channel Data Transfer .. 36 Figure 48 PCM Mode Single-channel Data Transfer .. 37 Figure 49 PCM Slave Mode Dual-channel Companded Data Transfer ... 37 Figure 50 SPI Timing Diagram .. 48 Figure 51 TWI Timing Diagram .. 49 Figure 52 SAI Timing Diagram .. 51 Figure 53 Digital Microphone Timing Diagram .. 51 Figure 54 Class D amplifier THD+N vs. Level 48ksps .. 52 Figure 55 Class D amplifier THD+N vs. Level 32ksps .. 52 Figure 56 Class D amplifier THD+N vs. Level 16ksps .. 53 Figure 57 Class D amplifier THD+N vs. Level 8ksps .. 53 Figure 58 Line out amplifier THD+N vs. Level 48/32/16/8ksps .. 54 Figure 59 Class D amplifier THD+N vs. Frequency 48ksps ... 55 Figure 60 Class D amplifier THD+N vs. Frequency 32ksps ... 55 Figure 61 Class D amplifier THD+N vs. Frequency 16ksps ... 56 Figure 62 Class D amplifier THD+N vs. Frequency 8ksps ... 56 Figure 63 Line out amplifier THD+N vs. Frequency 48/32/16/8ksps ... 57 Figure 64 Class D amplifier efficiency 4Ω ... 57 Figure 65 Class D Amplifier Efficiency 8Ω .. 58 Figure 66 Low Pass Filter Response Speaker Channel ... 58 Figure 67 High Pass Filter Response Speaker Channel ... 59 Figure 68 Low Pass Filter response Microphone Channels .. 60 Figure 69 High Pass Filter Response Microphone Channels .. 61 Figure 70 VQFN-24 Mechanical Outline (Q6)... 62 HistoryVersion ChangesDate 1 Document title changed to “CMX655D/CMX655A Ultra Low-Power Codec” 8th August 2018 Section 7.2 – Typical Performance Characteristics graphs added Section 5.6.7 – Automatic Level Control: description and associated register tables “greyed out” pending further revision 2 Revised performance figures 3rd September 2018 3 First public release 19th October 2018 4 All references to CMX655A removed 22nd October 2019 This is Provisional Information; changes and additions may be made to this specification. Parameters marked TBD or left blank will be included in later issues. Items that are highlighted or greyed out should be ignored. These will be clarified in later issues of this document. 2019 CML Microsystems Plc 4 D/655/4 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655D 3 Pin List 3.1 CMX655D 4 External Components 4.1 CMX655D 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Noise Gate 5.6.2.1 Noise Gate Registers 5.6.3 Record Level Detection 5.6.3.1 Record Level Detection Registers 5.6.4 Playback Preamplifier Gain 5.6.4.1 Playback Preamplifier Gain Register 5.6.5 Playback Volume Control 5.6.5.1 Playback Volume Register 5.6.6 Automatic Level Control 5.6.6.1 ALC Registers 5.6.7 Digital Sidetone 5.6.7.1 Digital Sidetone Register 5.6.8 Voice Filters 5.6.8.1 Low Pass Filter 5.6.8.2 DC Blocking Filter 5.6.8.3 High Pass Filter 5.6.8.4 Voice Filters Registers 5.6.9 Channel Multiplexing 5.6.10 Click-and-Pop Reduction 5.6.10.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 Configuration 6.1.3 Enable Audio Channels 6.1.4 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D End of Document cmlmicro.com CMX655D - Ultra-low Power Voice Codec - CML Micro
