Datasheet STSPIN32F0251, STSPIN32F0252 (STMicroelectronics) - 9

STSPIN32F0251, STSPIN32F0252 Electrical data 3.2 Thermal data Table 5. Thermal data Symbol Parameter Value Unit
Rth(JA) Thermal resistance junction to ambient(1) 27.6 °C/W 1. JEDEC 2s2p PCB in still air.
3.3 Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Test Condition Min. Typ. Max. Unit
VCC Power supply voltage (VCCthON)MAX 20 V V (1) Low-side driver supply LS 4 20 V voltage V (2) PS Low-side driver ground -5 5 V V (3) BO Floating supply voltage (VBOthON)MAX 20 V Comparator input VCIN 0 15 V voltage VOUT DC Output voltage -10(4) 230 V Maximum switching FSW frequency(5) 800 kHz Standard MCU VDD 3.0 3.3 3.6 V operating voltage MCU analog operating VDD 3.6 V voltage (ADC not used) Must have a potential VDDA equal to or higher than MCU analog operating VDD VDD 3.6 V voltage (ADC used) Operating junction TJ -40 125 °C temperature 1. VLS = VCC - VPGND 2. VPS = VPGND - VSGND 3. VBO = VBOOT - VOUT 4. LVG off. VCC = 9 V. Logic is operational if VBOOT > 5 V. 5. Actual maximum FSW depends on power dissipation. DS13048 Rev 2 9/29 29 Document Outline 1 Block diagram Figure 1. STSPIN32F025x SiP block diagram 2 Pin description and connection diagram Figure 2. STSPIN32F025x pin connection (Top view) Table 1. Legend/abbreviations used in the pin description table Table 2. Pin description Table 3. STSPIN32F025x MCU-Driver internal connections 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings 3.2 Thermal data Table 5. Thermal data 3.3 Recommended operating conditions Table 6. Recommended operating conditions 4 Electrical characteristics Table 7. Electrical characteristics Figure 3. Propagation delay timing definition Figure 4. Deadtime timing definitions Figure 5. Deadtime and interlocking waveforms definition 5 Device description 5.1 Gate driver 5.1.1 Inputs and outputs Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) 5.1.2 Deadtime 5.1.3 VCC UVLO protection Figure 6. VCC power ON and UVLO, LVG timing Figure 7. VCC power ON and UVLO, HVG timing 5.1.4 VBO UVLO protection Figure 8. VBO Power-ON and UVLO timing 5.1.5 Comparator and Smart shutdown Figure 9. Smart shutdown timing waveforms 5.2 Microcontroller unit 5.2.1 Memories and boot mode 5.2.2 Power management 5.2.3 High-speed external clock source Figure 10. Typical application with 8 MHz crystal Figure 11. HSE clock source timing diagram 5.3 Advanced-control timer (TIM1) Table 9. TIM1 channel configuration 6 Package information 6.1 TQFP 10x10 64L package information Figure 12. TQFP mechanical data Table 10. TQFP package dimensions 6.2 Suggested land pattern Figure 13. TQFP 10x10 64L suggested land pattern 7 Ordering information Table 11. Order codes 8 Revision history Table 12. Document revision history