Datasheet SSM2603 (Analog Devices) - 15

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Data Sheet SSM2603 DIGITAL AUDIO INTERFACE Digital Audio Data Sampling Rate
The digital audio input can support the following four digital audio To accommodate a wide variety of commonly used DAC and communication protocols: right-justified mode, left-justified mode, ADC sampling rates, the SSM2603 al ows for two modes of I2S mode, and digital signal processor (DSP) mode. operation, normal and USB, selected by the USB bit (Register R8, The mode selection is performed by writing to the FORMAT bits Bit D0). of the digital audio interface register (Register R7, Bit D1 and In normal mode, the SSM2603 supports digital audio sampling Bit D0). Al modes are MSB first and operate with data of 16 to rates from 8 kHz to 96 kHz. Normal mode supports 256 fS and 32 bits. 384 fS based clocks. To select the desired sampling rate, the user
Recording Mode
must set the appropriate sampling rate register in the SR control bits (Register R8, Bit D2 to Bit D5) and match this selection to the On the RECDAT output pin, the digital audio interface can core clock frequency that is pulsed on the MCLK pin. See Table 29 send digital audio data for recording mode operation. The and Table 30 for guidelines. digital audio interface outputs the processed internal ADC digital filter data onto the RECDAT output. The digital audio In USB mode, the SSM2603 supports digital audio sampling rates data stream on RECDAT comprises left- and right-channel from 8 kHz to 96 kHz. USB mode supports 250 fS and 272 fS audio data that is time domain multiplexed. based clocks. USB mode is enabled on the SSM2603 to support the common universal serial bus (USB) clock rate of 12 MHz, The RECLRC is the digital audio frame clock signal that separates or to support 24 MHz if the CLKDIV2 control register bit is left- and right-channel data on the RECDAT lines. activated. The user must set the appropriate sampling rate in The BCLK signal acts as the digital audio clock. Depending on the SR control bits (Register R8, Bit D2 to Bit D5). See Table 29 if the SSM2603 is in master or slave mode, the BCLK signal is and Table 31 for guidelines. either an input or an output signal. During a recording operation, Note that the sampling rate is generated as a fixed divider from RECDAT and RECLRC must be synchronous to the BCLK signal the MCLK signal. Because all audio processing references the to avoid data corruption. core MCLK signal, corruption of this signal, in turn, corrupts
Playback Mode
the outgoing audio quality of the SSM2603. The BCLK/RECLRC/ On the PBDAT input pin, the digital audio interface can receive RECDAT or BCLK/PBLRC/PBDAT signals must be synchronized digital audio data for playback mode operation. The digital audio with MCLK in the digital audio interface circuit. MCLK must data stream on PBDAT comprises left- and right-channel audio be faster or equal to the BCLK frequency to guarantee that no data that is time domain multiplexed. The PBLRC is the digital data is lost during data synchronization. audio frame clock signal that separates left- and right-channel The BCLK frequency should be greater than data on the PBDAT lines. Sampling Rate × Word Length × 2 The BCLK signal acts as the digital audio clock. Depending on Ensuring that the BCLK frequency is greater than this value whether the SSM2603 is in master or slave mode, the BCLK guarantees that all valid data bits are captured by the digital audio signal is either an input or an output signal. During a playback interface circuitry. For example, if a 32 kHz digital audio sampling operation, PBDAT and PBLRC must be synchronous to the rate with a 32-bit word length is desired, BCLK ≥ 2.048 MHz. BCLK signal to avoid data corruption.
1/fS LEFT CHANNEL RIGHT CHANNEL RECLRC/ PBLRC BCLK RECDAT/ 1 2 3 4 N X X 1 2 3 N X X PBDAT
013
X = DON’T CARE.
07241- Figure 23. Left-Justified Audio Input Mode Rev. D | Page 15 of 31 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core Clock ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Hardware Mute Pin Automatic Level Control (ALC) Decay (Gain Ramp-Up) Time Attack (Gain Ramp-Down) Time Noise Gate Analog Interface Signal Chain Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Left-Channel DAC Volume, Address 0x02 Right-Channel DAC Volume, Address 0x03 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F ALC Control 1, Address 0x10 ALC Control 2, Address 0x11 Noise Gate, Address 0x12 Outline Dimensions Ordering Guide