Datasheet AD74111 (Analog Devices) - 8

AD74111 78 90 74 88 70 86 dB 66 84 THD+N – THD+N – dB 62 82 58 80 54 78 84 16 24 32 40 48 8 16 24 32 40 48 SAMPLE RATE – kHz SAMPLE RATE – kHz
TPC 7. ADC THD+N vs. Sample Rate TPC 8. DAC THD+N vs. Sample Rate
FUNCTIONAL DESCRIPTION ADC Section General Description
The AD74111 contains a multibit sigma-delta ADC. The ADC The AD74111 is a 2.5 V mono codec. It comprises an ADC and has a single input pin with additional pins for decoupling/filter DAC channel with single-ended input and output. The ADC capacitors. The ADC channel has an independent input amplifier has a programmable gain stage and the DAC has programmable gain stage that can be programmed in steps of 3 dB, from 0 dB volume control. Each of these sections is described in further to 12 dB. The input amplifier gain settings are set by program- detail below. The AD74111 is controlled by means of a flexible ming the appropriate bits in Control Register E. The ADC can serial port (SPORT) that can be programmed to accommodate also be muted under software control. The AD74111 input many industry standard DSPs and microcontrollers. The AD74111 channel employs a multibit sigma-delta conversion technique that can be set to operate as a master or slave device. The AD74111 provides a high resolution output with system filtering imple- can be set to operate with sample rates of 8 kHz to 48 kHz, mented on-chip. Sigma-delta converters employ a technique depending on the values of MCLK and the MCLK prescalers. known as oversampling, where the sampling rate is many times On-chip digital filtering is provided as part of the DAC and the highest frequency of interest. In the case of the AD74111, ADC channels with a low group delay option to reduce the delays the oversampling ratio is 64 and a decimation filter is used to through the filters when operating at lower sample rates. Figure 4 reduce the output to standard sample rates. The maximum sample shows a block diagram of the DAC and ADC channel in the rate is 48 kHz. AD74111. Figures 5a and 5b show block diagrams of the filter arrangements of the ADC and DAC filters.
MCLK ADC INPUT PRESCALERS - ADC DECIMATOR ADC /4 SINC FILTER (/1 to /12) MODULATOR (/8) (/8) DATA 16-/20-/24- BITS ADC MODULATOR CLOCK - DAC DAC O/P /2 MODULATOR DAC MODULATOR CLOCK 5 BITS DAC INTERPOLATOR INTERPOLATOR DATA ( 16) ( 8) 16-/20-/24- BITS
Figure 4. ADC and DAC Engine –8– REV. 0 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS TEMPERATURE RANGE ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics FUNCTIONAL DESCRIPTION General Description ADC Section ADC, CAPP, and CAPN Pins Peak Readback Decimator Section Input Signal Swing DAC Section Output Signal Swing Low Group Delay Reference Master Clocking Scheme Selecting Sample Rates Resetting the AD74111 Power Supplies and Grounds Accessing the Internal Registers Serial Port Serial Port Operating Modes Mixed Mode Data Mode Data-Word Length Selecting Master or Slave Mode Master Mode Operation Slave Mode Operation OUTLINE DIMENSIONS