Datasheet AD73322L (Analog Devices)

Low Cost, Low Power CMOS General-Purpose Dual Analog Front End AD73322L FEATURES FUNCTIONAL BLOCK DIAGRAM Two 16-bit A/D converters AVDD1 AVDD2 DVDD Two 16-bit D/A converters AD73322L Programmable input/output sample rates VFBP1 SDI 78 dB ADC SNR VINP1 ADC CHANNEL 1 VINN1 SDIFS 78 dB DAC SNR VFBN1 64 kHz maximum sample rate VOUTP1 DAC CHANNEL 1 SCLK −90 dB crosstalk VOUTN1 Low group delay (25 µs typ per ADC channel, 50 µs typ per REFOUT SE DAC channel) REFERENCE SPORT REFCAP RESET Programmable input/output gain VFBP2 Flexible serial port allows up to 4 dual codecs to be VINP2 ADC CHANNEL 2 MCLK VINN2 connected in cascade, giving 8 I/O channels VFBN2 Single-supply operation (2.7 V to 3.3 V) VOUTP2 SDOFS 50 mW typ power consumption at 3.0 V DAC CHANNEL 2 VOUTN2 SDO Temperature range: −40°C to +105°C On-chip reference AGND1 AGND2 DGND
00691-001
28-lead SOIC, TSSOP, and 44-lead LQFP packages APPLICATIONS
Figure 1.
General-purpose analog I/O Speech processing Cordless and personal communications Telephony Active control of sound and vibration Data communications Wireless local loop GENERAL DESCRIPTION
The AD73322L is a dual front-end processor for general- The A/D and D/A conversion channels feature programmable purpose applications, including speech and telephony. It input/output gains with ranges of 38 dB and 21 dB, respectively. features two 16-bit A/D conversion channels and two 16-bit An on-chip reference voltage allows single-supply operation. D/A conversion channels. Each channel provides 78 dB signal- to-noise ratio over a voice-band signal bandwidth. It also The sampling rate of the codecs is programmable with four features an input-to-output gain network in both the analog separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz and digital domains. This is featured on both codecs and can sampling rates (from a master clock of 16.384 MHz). be used for impedance matching or scaling when interfacing to A serial port (SPORT) allows easy interfacing of single or subscriber line interface circuits (SLICs). cascaded devices to industry-standard DSP engines. The The AD73322L is particularly suitable for a variety of appli- SPORT transfer rate is programmable to allow interfacing to cations in the speech and telephony area, including low bit rate, both fast and slow DSP engines. high quality compression, speech enhancement, recognition, The AD73322L is available in 28-lead SOIC, 28-lead TSSOP, and synthesis. The low group delay characteristic of the part and 44-lead LQFP packages. makes it suitable for single or multichannel active control applications.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE