A product Line of Diodes Incorporated PI6CG33402Pin Description Cont.Pin #Pin NameTypeDescription 17 OE1# Input CMOS Active low input for enabling Q1 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 18 Q1+ Output HCSL Differential true clock output 19 Q1- Output HCSL Differential complementary clock output 20 GNDA Power — Ground for analog circuitry 21 VDDA Power — Power supply for analog circuitry 22 Q2+ Output HCSL Differential true clock output 23 Q2- Output HCSL Differential complementary clock output 24 OE2# Input CMOS Active low input for enabling Q2 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 27 Q3+ Output HCSL Differential true clock output 28 Q3- Output HCSL Differential complementary clock output 29 OE3# Input CMOS Active low input for enabling Q3 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs Input notifies device to sample latched inputs and start up on first high 31 PD# Input CMOS assertion. Low enters Power Down Mode, and subsequent high assertions exit Power Down Mode. This pin has internal pullup resistor. 32 SS_SEL_TRI Input Tri-level Latched select input to select spread spectrum amount at initial power up. 1 = -0.5% spread, M = -0.25%, 0 = Spread Off Epad GND Power — Connect to ground PI6CG33402 www.diodes.com May 2019 Document Number DS41073 Rev 3-2 3 Diodes Incorporated
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