Datasheet ADT7301 (Analog Devices) - 4

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ADT7301 TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 2. Parameter1 Limit Unit Comments
t 5 ns min 1 CS to SCLK setup time t 25 ns min SCLK high pulse width 2 t 25 ns min SCLK low pulse width 3 t 2 35 ns max Data access time after SCLK falling edge 4 t 20 ns min Data setup time prior to SCLK rising edge 5 t 5 ns min Data hold time after SCLK rising edge 6 t 5 ns min 7 CS to SCLK hold time t 2 40 ns max 8 CS to DOUT high Impedance 1 See Figure 14 for the SPI timing diagram. 2 Measured with the load circuit of Figure 2.
200
µ
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
µ
A IOH
02884-0-002 Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time Rev. B | Page 4 of 16 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Converter Details Temperature Value Register Temperature Conversion Equations Serial Interface Read Operation Write Operation Applications Information Microprocessor Interfacing ADT7301-to-MC68HC11 Interface ADT7301-to-8051 Interface ADT7301-to-PIC16C6x/7x Interface ADT7301-to-ADSP-21xx Interface Mounting the ADT7301 Supply Decoupling Outline Dimensions Ordering Guide