link to page 5 link to page 5 link to page 5 ADT7517-KGDKnown Good DieParameterMinTypMaxUnitTest Conditions/Comments CONVERSION TIMES Single-channel mode Slow ADC VDD/AIN 11.4 ms Averaging (16 samples) on 712 µs Averaging off Internal Temperature 11.4 ms Averaging (16 samples) on 712 µs Averaging off External Temperature 24.22 ms Averaging (16 samples) on 1.51 ms Averaging off Fast ADC VDD/AIN 712 µs Averaging (16 samples) on 44.5 µs Averaging off Internal Temperature 2.14 ms Averaging (16 samples) on 134 µs Averaging off External Temperature 14.25 ms Averaging (16 samples) on 890 µs Averaging off ROUND ROBIN UPDATE RATE4 Time to complete one measurement cycle through all channels Slow ADC at 25°C Averaging On 79.8 ms AIN1 and AIN2 are selected on Pad 8 and Pad 9 Averaging Off 4.99 ms AIN1 and AIN2 are selected on Pad 8 and Pad 9 Averaging On 94.76 ms D+ and D− are selected on Pad 8 and Pad 9 Averaging Off 9.26 ms D+ and D− are selected on Pad 8 and Pad 9 Fast ADC at 25°C Averaging On 6.41 ms AIN1 and AIN2 are selected on Pad 8 and Pad 9 Averaging Off 400.84 µs AIN1 and AIN2 are selected on Pad 8 and Pad 9 Averaging On 21.77 ms D+ and D− are selected on Pad 8 and Pad 9 Averaging Off 3.07 ms D+ and D− are selected on Pad 8 and Pad 9 DAC EXTERNAL REFERENCE INPUT3 VREF Input Range 1 VDD V Buffered reference VREF Input Impedance >10 MΩ Buffered reference and power-down mode Reference Feedthrough −90 dB Frequency = 10 kHz Channel-to-Channel Isolation −75 dB Frequency = 10 kHz ON-CHIP REFERENCE3 Reference Voltage 2.2662 2.28 2.2938 V Temperature Coefficient 80 ppm/°C OUTPUT CHARACTERISTICS3 Output Voltage5 0.001 VDD − 0.1 V This is a measure of the minimum and maximum drive capability of the output amplifier DC Output Impedance 0.5 Ω Short-Circuit Current 25 mA VDD = 5 V 16 mA VDD = 3 V Power-Up Time 2.5 µs Coming out of power-down mode, VDD = 5 V 5 µs Coming out of power-down mode, VDD = 3.3 V DIGITAL INPUTS3 Input Current ±1 µA VIN = 0 V to VDD Input Low Voltage, VIL 0.8 V Input High Voltage, VIH 1.89 V Pad Capacitance 3 10 pF All digital inputs SCL, SDA Glitch Rejection 50 ns Input filtering suppresses noise spikes of less than 50 ns LDAC Pulse Width 20 ns Edge triggered input Rev. A | Page 4 of 11 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DAC AC CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE
