link to page 7 link to page 7 link to page 7 Known Good DieADT7517-KGDParameterMinTypMaxUnitTest Conditions/Comments DIGITAL OUTPUT Output High Voltage, VOH 2.4 V ISOURCE = ISINK = 200 µA Output Low Voltage, VOL 0.4 V IOL = 3 mA Output High Current, IOH 1 mA VOH = 5 V Output Capacitance, COUT 50 pF INT/INT Output Saturation Voltage 0.8 V IOUT = 4 mA I2C TIMING CHARACTERISTICS6, 7 See Figure 2 Serial Clock Period, t1 2.5 µs Fast mode I2C Data In Setup Time to SCL High, t2 50 ns Data Out Stable After SCL Low, t3 0 ns SDA Low Setup Time to SCL Low 50 ns (Start Condition), t4 SDA High Hold Time After SCL High 50 ns (Stop Condition), t5 SDA and SCL Fall Time, t6 300 ns SDA and SCL Rise Time, t7 3008 ns SPI TIMING CHARACTERISTICS3, 9 See Figure 3 CS to SCLK Setup Time, t1 0 ns SCLK High Pulse Width, t2 50 ns SCLK Low Pulse Width, t3 50 ns Data Access Time After SCLK 35 ns Falling Edge, t 10 4 Data Setup Time Prior to SCLK 20 ns Rising Edge, t5 Data Hold Time After SCLK 0 ns Rising Edge, t6 CS to SCLK Hold Time, t7 0 µs CS to DOUT High Impedance, t8 40 ns POWER REQUIREMENTS VDD 2.7 5.5 V VDD Settling Time 50 ms VDD settles to within 10% of its final voltage level IDD (Normal Mode)11 3 mA VDD = 3.3 V, VIH = VDD, and VIL = GND 2.2 3 mA VDD = 5 V, VIH = VDD, and VIL = GND IDD (Power-Down Mode) 10 µA VDD = 3.3 V, VIH = VDD, and VIL = GND 10 µA VDD = 5 V, VIH = VDD, and VIL = GND Power Dissipation 10 mW VDD = 3.3 V, normal mode 33 µW VDD = 3.3 V, shutdown mode 1 DC specifications are tested with the outputs unloaded. 2 Linearity is tested using a reduced code range: Code 28 to Code 1023. 3 Guaranteed by design and characterization; not production tested. 4 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4. 5 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (VREF = VDD), the offset error plus gain error must be positive. 6 The SDA and SCL timing is measured with the input filters turned on to meet the fast mode I2C specification. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part. 7 Guaranteed by design; not production tested. All I2C timing specifications are for fast mode operation, but the interface is still capable of handling the slower standard rate specifications. 8 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns. 9 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 10 Measured with the load circuit shown in Figure 4. 11 The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded. Rev. A | Page 5 of 11 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DAC AC CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE
