Datasheet PHK12NQ03LT (Nexperia) - 3

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Philips Semiconductors PHK12NQ03LT N-channel TrenchMOS™ logic level FET 4. Limiting values Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V ≤ DS drain-source voltage (DC) 25 °C ≤ Tj 150 °C - 30 V VGS gate-source voltage - ±20 V I ≤ D drain current Tamb = 25 °C; pulsed; tp 10 s; Figure 2 and 3 - 11.8 A I ≤ DM peak drain current Tamb = 25 °C; pulsed; tp 10 µs; Figure 3 - 35.3 A P ≤ tot total power dissipation Tamb = 25 °C; pulsed; tp 10 s; Figure 1 - 2.5 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C
Source-drain diode
I ≤ S source (diode forward) current Tamb = 25 °C; pulsed; tp 10 s - 11.8 A
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source unclamped inductive load; ID = 7.7 A; - 440 mJ avalanche energy tp = 2.35 ms; VDD ≤ 30 V; VGS = 10 V; starting Tj = 25 °C 9397 750 12955 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data Rev. 02 — 02 March 2004 2 of 12
Document Outline 1. Product profile 1.1 Description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 5.1 Transient thermal impedance 6. Characteristics 7. Package outline 8. Revision history 9. Data sheet status 10. Definitions 11. Disclaimers 12. Trademarks