Datasheet ADA4254 (Analog Devices) - 29

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Data Sheet ADA4254 CS DIGITAL CS SUPPLY ADuCM4050 SCLK SCLK ADA4254 MOSI SDI 10kΩ 10kΩ MISO OR SDO GPIO/SCS ADuM141E OR ADuM141D CS SCLK ADC SDI SDO CS SCLK DAC SDI
57 -0
SDO
741 15 Figure 87. Typical SCS Implementation with Devices Without SDO Tristate Support
CS DIGITAL CS SUPPLY ADuCM4050 SCLK SCLK ADA4254 MOSI SDI 10kΩ 10kΩ MISO SDO GPIO/SCS ADuM141E OR ADuM141D CS SCLK SDI ADC SDO CS SCLK SDI DAC
56 -0
SDO
741 15 Figure 88. Typical SCS Implementation with All Devices Supporting SDO Tristate When configured for SCS, communication with the ADA4254 and all slave devices follows a predefined pattern. The first CS
0 CS
pulse is passed to the first GPIO that is set up for SCS,
4 GPIO0/SCS0
effectively communicating with the first slave device.
5 GPIO1/SCS1
Subsequent CS pulses progress through any GPIOs configured
3 SCK
for SCS in ascending order. The last CS pulse addresses the
2 SDO
ADA4254 itself. This pattern repeats until SCS is disabled.
1 SDI
Figure 87 and Figure 88 show the ADA4254 operating in SCS mode with GPIO0 and GPIO1 communicating with two slave devices. GPIO0 is connected to the CS line of an ADC. GPIO1 is connected to the CS line of a DAC.
M10.0µs A CH1 340V
058 In Figure 89, five distinct CS pulses can be seen. The first CS 41-
T 26.72000µs
157 pulse writes 0x03 to the GPIO_DIR register to configure GPIO0 Figure 89. SCS Configuration and Operation with Two Slave Devices and GPIO1 as outputs. The second CS pulse writes 0x03 to SCS to configure GPIO0 and GPIO1 for SCS. The third CS pulse is replicated on GPIO0 and communicates with the first slave device, an ADC in this case. The fourth CS pulse is replicated on GPIO1 and communicates with the second slave device, a DAC in this case. The fifth CS pulse communicates with the ADA4254 itself. This pattern of communication continues in order of ADC, DAC, and ADA4254 until SCS is changed. Rev. A | Page 29 of 59 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM COMPANION PRODUCTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER INPUT MULTIPLEXER EMI REDUCTION AND INTERNAL EMI FILTER INPUT AMPLIFIER OUTPUT AMPLIFIER POWER SUPPLIES ESD MAP OUTPUT RIPPLE CALIBRATION CONFIGURATION GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs) EXCITATION CURRENTS EXTERNAL CLOCK SYNCHRONIZATION SEQUENTIAL CHIP SELECT (SCS) GAIN ERROR CALIBRATION WIRE BREAK DETECTION TEST MULTIPLEXER EXTERNAL MUX CONTROL DIGITAL INTERFACE SPI INTERFACE ACCESSING THE ADA4254 REGISTER MAP CHECKSUM PROTECTION CRC CALCULATION MEMORY MAP CHECKSUM PROTECTION READ-ONLY MEMORY (ROM) CHECKSUM PROTECTION SPI READ/WRITE ERROR DETECTION SPI COMMAND LENGTH ERROR DETECTION APPLICATIONS INFORMATION INPUT AND OUTPUT OFFSET VOLTAGE AND NOISE ADC CLOCK SYNCHRONIZATION PROGRAMMABLE LOGIC CONTROLLER (PLC)VOLTAGE/CURRENT INPUT 3-WIRE RTD WITH CURRENT EXCITATION HIGH RAIL CURRENT SENSING REGISTER SUMMARY REGISTER DETAILS GAIN_MUX REGISTER DETAILS Bit 7, G4—Output Amplifier Scaling Gain (1.375 V/V) Bits[6:3], G[3:0]—Input Amplifier Gain Setting Bits[1:0], EXT_MUX[1:0]—External Multiplexer Control SOFTWARE RESET REGISTER (RESET) DETAILS Bit 0, RST—Soft Reset CLOCK SYNCHRONIZATION CONFIGURATION REGISTER (SYNC_CFG) DETAILS Bit 6, CLK_OUT_SEL—Clock Output Select Bit 4, SYNC_POL—Clock Synchronization Polarity Bits[2:0], SYNC[2:0]—Internal Clock Divider Value DIGITAL ERROR REGISTER (DIGITAL_ERR) DETAILS Bit 6, CAL_BUSY—Calibration Busy (Read Only) Bit 5, SPI_CRC_ERR—SPI CRC Error Bit 4, SPI_RW_ERR—SPI Read/Write Error Bit 3, SPI_SCLK_CNT_ERR—SPI SCLK Count Error Bit 1, MM_CRC_ERR—Memory Map CRC Error Bit 0, ROM_CRC_ERR—ROM CRC Error ANALOG ERROR REGISTER (ANALOG_ERR) DETAILS Bit 7, G_RST—Gain Reset Flag Bit 6, POR_HV—Power-On Reset HV Supply Bit 4, WB_ERR—Wire Break Detect Error Bit 3, FAULT_INT—Fault Interrupt Bit 2, OUTPUT_ERR—Output Amplifier Error Bit 1, INPUT_ERR—Input Amplifier Error Bit 0, MUX_OVER_VOLT_ERR—Input Multiplexer Overvoltage Error GPIO DATA REGISTER (GPIO_DATA) DETAILS Bits[6:0], GPIO_DATA[6:0]—GPIO Data Values INTERNAL MUX CONTROL REGISTER (INPUT_MUX) DETAILS Bit 6, SW_A1, and Bit 5, SW_A2—Channel 1 Input Switches Bit 4, SW_B1, and Bit 3, SW_B2—Channel 2 Input Switches Bit 2, SW_C1, and Bit 1, SW_C2—PGIA Input Test Multiplexer Switches Bit 0, SW_D12—PGIA Input Short Switch WIRE BREAK DETECT REGISTER (WB_DETECT) DETAILS Bit 7, WB_G_RST_DIS—Wire Break Gain Reset Disable Bit 3, SW_F1, and Bit 2, SW_F2—Fault Switch Selection Bits[1:0], WB_CURRENT—Detection Current Selection GPIO DIRECTION REGISTER (GPIO_DIR) DETAILS Bits[6:0], GPIO_DIR—GPIO Direction Configuration SEQUENTIAL CHIP SELECT REGISTER (SCS) DETAILS Bits[6:0], SCS—Sequential Chip Select Configuration ANALOG ERROR MASK REGISTER (ANALOG_ERR_DIS) DETAILS Bit 7, G_RST_DIS—Disable Gain Reset Error Flag Bit 6, POR_HV_DIS—Disable High Voltage Power Reset Flag Bit 4, WB_ERR_DIS—Disable Wire-Break Detection Flag Bit 3, MUX_PROT_DIS—Disable Input Multiplexer Protection Bit 2, OUTPUT_ERR_DIS—Disable Output Amplifier Error Flag Bit 1, INPUT_ERR_DIS—Disable Input Amplifier Error Flag Bit 0, MUX_OVER_VOLT_ERR_DIS—Disable Multiplexer Overvoltage Flag. DIGITAL ERROR MASK REGISTER (DIGITAL_ERR_DIS) DETAILS Bit 6, CAL_BUSY_DIS—Disable Calibration Busy Error Flag Bit 5, SPI_CRC_ERR_DIS—Disable SPI CRC Error Flag Bit 4, SPI_RW_ERR_DIS—Disable SPI Read/Write Error Flag Bit 3, SPI_SCLK_CNT_ERR_DIS—Disable SPI SCLK Count Error Flag Bit 2, M_CLK_CNT_ERR_DIS—Disable Master Clock Count Output Bit 1, MM_CRC_ERR_DIS—Disable Memory Map CRC Error Flag Bit 0, ROM_CRC_ERR_DIS—Disable ROM CRC Error Flag SPECIAL FUNCTION CONFIGURATION REGISTER (SF_CFG) DETAILS Bit 5, INT_CLK_OUT—Internal Oscillator Output Bit 4, EXT_CLK_IN—External Oscillator Input Bit 3, FAULT_INT_OUT—Fault Interrupt Output Bit 2, CAL_BUSY_OUT—Calibration Busy Output Bits[1:0], EXT_MUX_EN[1:0]—Enable External Multiplexer Control ERROR CONFIGURATION REGISTER Bit 7, ERR_LATCH_DIS—Disable Error Latching Bits[3:0], ERR_DELAY[3:0] —Error Suppression Time TEST MULTIPLEXER REGISTER (TEST_MUX) DETAILS Bit 7, G5—Output Amplifier Scaling Gain = 1.25 V/V Bit 6, CAL_SEL—Calibration Type Configuration Bits[5:4], CAL_EN[1:0]—Scheduled Calibration Enable and Interval Bits[3:0], TEST_MUX[3:0]—Input Test Multiplexer Configuration EXCITATION CURRENT CONFIGURATION REGISTER (EX_CURRENT_CFG) DETAILS Bits[7:6], EX_CURRENT_SEL[1:0]—Excitation Current Connection Configuration Bits[3:0], EX_CURRENT[3:0]—Excitation Current Value GAIN CALIBRATION REGISTERS (GAIN_CALx) DETAILS TRIGGER CALIBRATION REGISTER (TRIG_CAL) DETAILS Bit 0, TRIG_CAL—Trigger Calibration Input MASTER CLOCK COUNT REGISTER (M_CLK_CNT) DETAILS Bits[7:0], M_CLK_CNT[7:0]—Master Clock Count DIE REVISION IDENTIFICATION REGISTER (DIE_REV_ID) DETAILS Bits[7:0], DIE_REV_ID[7:0]—Die Revision Identification Number DEVICE IDENTIFICATION REGISTERS (PART_ID) DETAILS PART_ID[39:0]—Part ID Number OUTLINE DIMENSIONS ORDERING GUIDE