Everest Semiconductor Confidential ES8311SCLK rising to SDIN hold time TSDIH 10 ns Note 1: one SCLK period of high time in DSP/PCM modes. Note 2: only apply to MSB of Left Justified or DSP/PCM mode B. LRCK TSLR TLSR TSCLKH TSCLKL SCLK TSDO TLDO SDOUT TSDIS TSDIH SDIN Figure 3 Serial Audio Port Timing
I2C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE)PARAMETER Symbol MIN MAX UNIT CCLK Clock Frequency FCCLK 100/400 KHz Bus Free Time Between Transmissions TTWID 4.7/1.3 us Start Condition Hold Time TTWSTH 4.0/0.6 us Clock Low time TTWCL 4.7/1.3 us Clock High Time TTWCH 4.0/0.6 us Setup Time for Repeated Start Condition TTWSTS 4.7/0.6 us CDATA Hold Time from CCLK Falling TTWDH 3.45/0.9 us CDATA Setup time to CCLK Rising TTWDS 0.25/0.1 us Rise Time of CCLK TTWR 1.0/0.3 us Fall Time CCLK TTWF 1.0/0.3 us Figure 4 I2C Timing Revision 7.0 10 January 2020 Latest datasheet: www.everest-semi.com or
[email protected] Document Outline Block Diagram Pin Out and Description typical APPLICATION CIRCUIT Clock Modes and Sampling Frequencies Micro-controller configuration Interface Digital Audio Interface ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Recommended Operating Conditions ADC Analog and Filter Characteristics and Specifications DAC Analog and Filter Characteristics and Specifications DC Characteristics Serial Audio Port Switching Specifications I2C Switching Specifications (slow speed mode/high speed mode) Package CORPORATe INFORMATION
