Datasheet SZ8463ML, SZ8463RL, SZ8463FML, SZ8463FML (Microchip) - 2

ПроизводительMicrochip
ОписаниеIEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII
Страниц / Страница213 / 2 — KSZ8463ML/RL/FML/FRL. Comprehensive Configuration Registers Access. …
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Язык документаанглийский

KSZ8463ML/RL/FML/FRL. Comprehensive Configuration Registers Access. Additional Features

KSZ8463ML/RL/FML/FRL Comprehensive Configuration Registers Access Additional Features

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IEEE 1588 3-port 10/100 Switch w/Generic host I/F & Fibre support 64 LQFP 10x10x1.4mm TRAY
Триема
Россия
KSZ8463FMLI
252 ₽
T-electron
Россия и страны СНГ
KSZ8463RLI
Microchip
326 ₽
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KSZ8463MLI-EVAL
32 057 ₽
KSZ8463RLI LQFP64 Интерфейс Ethernet
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KSZ8463ML/RL/FML/FRL Comprehensive Configuration Registers Access
• Energy Detect Power-Down (EDPD), which Dis- • High-Speed SPI (4-Wire, Up to 50 MHz) Interface ables the PHY Transceiver when Cables are to Access All Internal Registers Removed • MII Management (MIIM, MDC/MDIO 2-Wire) • Dynamic Clock Tree Control to Reduce Clocking Interface to Access All PHY Registers per Clause in Areas Not in Use 22.2.4.5 of the IEEE 802.3 Specification • Power Consumption Less than 0.5W • I/O Pin Strapping Facility to Set Certain Register
Additional Features
Bits from I/O Pins at Reset Time • Single 25 MHz ±50 ppm Reference Clock • Control Registers Configurable On-the-Fly Requirement for MII Mode
IEEE 1588v2 PTP and Clock Synchronization
• Selectable 25 MHz or 50 MHz Inputs for RMII • Fully Compliant with the IEEE 1588v2 Precision Mode Time Protocol • Comprehensive Programmable Two LED Indica- • One-Step or Two-Step Transparent Clock (TC) tors Support for Link, Activity, Full-/Half-Duplex Timing Corrections and 10/100 Speed • E2E (End-to-End) or P2P (Peer-to-Peer) Trans- • LED Pins Directly Controllable parent Clock (TC) • Industrial Temperature Range: –40°C to +85°C • Grandmaster, Master, Slave, Ordinary Clock (OC) • 64-Pin (10 mm x 10 mm) Lead Free (ROHS) Support LQFP Package • IEEE1588v2 PTP Multicast and Unicast Frame
Applications
Support • Industrial Ethernet Applications that Employ IEEE • Transports of PTP Over IPv4/IPv6 UDP and IEEE 802.3-Compliant MACs. (Ethernet/IP, Profinet, 802.3 Ethernet MODBUS TCP, etc) • Delay Request-Response and Peer Delay Mech- • Real-Time Ethernet Networks Requiring Sub- anism Microsecond Synchronization over Standard • Ingress/Egress Packet time stamp Capture/ Ethernet Recording and Checksum Update • IEC 61850 Networks Supporting Power Substa- • Correction Field Update with Residence Time and tion Automation Link Delay • Networked Measurement and Control Systems • IEEE1588v2 PTP Packet Filtering Unit to Reduce • Industrial Automation and Motion Control Sys- Host Processor Overhead tems • A 64-bit Adjustable System Precision Clock • Test and Measurement Equipment • Twelve Trigger Output Units and Twelve time stamp Input Units Available for Flexible IEEE1588v2 Control of Twelve Programmable GPIO[11:0] Pins Synchronized to the Precision Time Clock • GPIO Pin Usage for 1 PPS Generation, Fre- quency Generator, Control Bit Streams, Event Monitoring, Precision Pulse Generation, Complex Waveform Generation
Power and Power Management
• Single 3.3V Power Supply with Optional VDD I/O for 1.8V, 2.5V, or 3.3V • Integrated Low Voltage (~1.3V) Low-Noise Regu- lator (LDO) Output for Digital and Analog Core Power • Supports IEEE P802.3az™ Energy Efficient Ethernet (EEE) to Reduce Power Consumption in Transceivers in LPI State • Full-Chip Hardware or Software Power-Down (All Registers Value are Not Saved and Strap-In Value will Re-Strap After Release the Power-Down) DS00002642A-page 2

 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
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