LinTai: качественные китайские корпуса и каркасы

Datasheet SZ8463ML, SZ8463RL, SZ8463FML, SZ8463FML (Microchip) - 7

ПроизводительMicrochip
ОписаниеIEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII
Страниц / Страница213 / 7 — KSZ8463ML/RL/FML/FRL. 1.2. General Description
Формат / Размер файлаPDF / 2.4 Мб
Язык документаанглийский

KSZ8463ML/RL/FML/FRL. 1.2. General Description

KSZ8463ML/RL/FML/FRL 1.2 General Description

Сравнительное тестирование аккумуляторов EVE Energy и Samsung типоразмера 18650

Модельный ряд для этого даташита

Текстовая версия документа

KSZ8463ML/RL/FML/FRL 1.2 General Description
The KSZ8463 EtherSynch® product line consists of IEEE 1588v2 enabled Ethernet switches, providing integrated com- munications and synchronization for a range of Industrial Ethernet applications. The KSZ8463 EtherSynch product line enables distributed, daisy-chained or ring topologies preferred for Industrial Ethernet networks. Conventional centralized (i.e., star-wired) topologies are also supported for dual-homed, fault-toler- ant arrangements. A flexible set of standard MAC interfaces is provided to interface to external host processors with embedded Ethernet MACs: • KSZ8463ML: Media Independent Interface (MII) • KSZ8463RL: Reduced Media Independent Interface (RMII) • KSZ8463FML: MII, supports 100BASE-FX fiber in addition to 10/100BASE-TX copper • KSZ8463FRL: RMII, supports 100BASE-FX fiber in addition to 10/100BASE-TX copper The KSZ8463 devices incorporate the IEEE 1588v2 protocol. Sub-microsecond synchronization is available via the use of hardware-based time-stamping and transparent clocks making it the ideal solution for time synchronized Layer 2 com- munication in critical industrial applications. Extensive general purpose I/O (GPIO) capabilities are available to use with the IEEE 1588v2 PTP to efficiently and accurately interface to locally connected devices. Complementing the industry’s most-integrated IEEE 1588v2 device is a precision timing protocol (PTP) v2 software stack that has been pre-qualified with the KSZ84xx product family. The PTP stack has been optimized around the KSZ84xx chip architecture, and is available in source code format along with Microchip’s chip driver. The KSZ8463 product line is built upon Microchip’s industry-leading Ethernet technology, with features designed to off- load host processing and streamline your overal design. • Wire-speed Ethernet switching fabric with extensive filtering • Two integrated 10/100BASE-TX PHY transceivers, featuring the industry’s lowest power consumption • Full-featured quality-of-service (QoS) support • Flexible management options that support common standard interfaces The wire-speed, store-and-forward switching fabric provides a full complement of QoS and congestion control features optimized for real-time Ethernet. A robust assortment of power-management features including Energy Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments.  2018 Microchip Technology Inc.

DS00002642A-page 7 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
Электронные компоненты. Бесплатная доставка по России