KSZ8463ML/RL/FML/FRLFIGURE 1-1:SYSTEM BLOCK DIAGRAM, KSZ8463ML/RL/FML/FRL 1024 FRAME MIB BUFFER QUEUE ADDRESSES BUFFERS COUNTERS MANAGEMENT MANAGEMENT LOOK-UP TABLE SWITCH ENGINE VLAN TAGGING, QoS PRIORITY, FIFO, FLOW CONTROL IEEE 1588 PTP PACKET FILTERING AND PROCESSING IEEE 1588 TIME STAMP FOR PORT 1 MII/RMII (PORT 3) IEEE 1588 ENABLED IEEE 1588 PORT 1 10/100 MAC3 10/100 BASE ENABLED TX/RX± T/TX/FX 10/100 SERIAL PORT SERIAL PORT PHY 1 I/O REGISTERS INTERFACE MAC 1 (AUTO MDI/MDI-X) CONTROL/STATUS 10/100 BASE SPI OR MIIM IEEE 1588 T/TX/FX ENABLED PORT 2 PHY 2 10/100 TX/RX± MAC 2 X1 (TO 1588 TIME PLL STAMP BLOCKS) X2 12 EVENT TRIGGER UNITS CLOCK IEEE 1588 TIME AND 12 TIMESTAMP UNITS STAMP FOR PORT 2 IEEE 1588 SYNCHRONIZED LINK MD AND CLOCK ENERGY EFFICIENT ETHERNET CONTROL GPIOs VDD_IO P1LED[1:0] 1.3V LOW-NOISE STRAP-IN LEDs REGULATOR CONFIGURATION DRIVER VDD_L P2LED[1:0] DS00002642A-page 8
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
