Datasheet KSZ8842-16M, KSZ8842-32M (Microchip) - 5

KSZ8842-16M/-32M 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: PIN CONFIGURATION FOR KSZ8842-16MQL
O N N 0 1 2 3 4 5 N T DDC DDI NC NC NC NC NC NC NC NC NC NC VDDIO V DGND NC BE0 BE1 NC NC A1 A2 A3 A4 A5 V DGND A6 A7 A8 A9 A1 A1 A1 A1 A1 A1 RS X2 X1 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 102 101 100 64 AGND NC 104 63 VDDAP NC 105 62 AGND NC 106 61 ISET NC 107 60 NC DGND 108 59 NC VDDIO 109 58 AGND NC 110 57 VDDA D15 111 56 TXP2 D14 112 55 TXM2 D13 113 54 AGND D12 114 53 RXP2 D11 D10 115 52 RXM2 D9 116 KSZ8842-16MQL 51 VDDARX D8 117 50 VDDATX (Top View) D7 118 49 TXM1 D6 119 48 TXP1 D5 120 47 AGND D4 121 46 RXM1 D3 122 45 RXP1 DGND 123 44 NC DGND 124 43 VDDA VDDIO 125 42 AGND D2 126 41 NC D1 127 40 NC D0 128 39 AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 1 0 O N D D2 D D D2 D N E E NC NC RDN EESK EEDI SWR AEN R DDA WRN 1LE 2LE BCLK ARDY EEEN EED ADSN V VDDIO SRDYN INTRN LDEVN EECS DGND DGND AG TESTEN SCANEN P P1L P1L P P2LED1 P2LED0 DGND P1LED3 CYCLEN P2LED3 VDDCO VLBUSN PW RDYRTNN  2020 Microchip Technology Inc. DS00003459A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service