KSZ8852HLE1.0INTRODUCTION1.1General Terms and Conditions The following is list of the general terms used throughout this document: BIU - Bus Interface Unit The host interface function that performs code conversion, buffering, and the like required for communications to and from a network. BPDU - Bridge Protocol Data Unit A packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination. CMOS - Complementary Metal Oxide A common semiconductor manufacturing technique in which positive Semiconductor and negative types of transistors are combined to form a current gate that in turn forms an effective means of controlling electrical current through a chip. CRC - Cyclic Redundancy Check A common technique for detecting data transmission errors. CRC for Ethernet is 32 bits long. Cut-Through Switch A switch typically processes received packets by reading in the full packet (storing), then processing the packet to determine where it needs to go, then forwarding it. A cut-through switch simply reads in the first bit of an incoming packet and forwards the packet. Cut- through switches do not store the packet. DA - Destination Address The network address to which packets are sent. DMA - Direct Memory Access A design in which memory on a chip is controlled independently of the CPU. EMI - Electromagnetic Interference A naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. In computer tech- nology, computer devices are susceptible to EMI because electro- magnetic fields are a byproduct of passing electricity through a wire. Data lines that have not been properly shielded are susceptible to data corruption by EMI. FCS - Frame Check Sequence See CRC. FID - Frame or Filter ID Specifies the frame identifier. Alternately is the filter identifier. IGMP - Internet Group Management The protocol defined by RFC 1112 for IP multicast transmissions. Protocol IPG - Inter-Packet Gap A time delay between successive data packets mandated by the net- work standard for protocol reasons. In Ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. IPG is used to correct timing differences between a transmitter and receiver. During the IPG, no data is transferred, and information in the gap can be discarded or additions inserted without impact on data integrity. ISA - Industry Standard Architecture A bus architecture used in the IBM PC/XT and PC/AT. ISI - Inter-Symbol Interference The disruption of transmitted code caused by adjacent pulses affect- ing or interfering with each other. Jumbo Packet A packet larger than the standard Ethernet packet (1500 bytes). Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. MAC - Media Access Controller A functional block responsible for implementing the Media Access Control layer which is a sub layer of the Data Link Layer. MDI - Medium Dependent Interface An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or cross- over, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore “media dependent”. 2018 Microchip Technology Inc.
DS00002761A-page 5 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 MDI/MDI−X Auto Crossover 3.4 Auto Negotiation 3.5 LINK MD® Cable Diagnostics 3.6 On-Chip Termination Resistors 3.7 Lookback Support 3.8 MAC (Media Access Controller) Block 3.9 Switch Block 3.10 IGMP Support 3.11 IPv6 MLD Snooping 3.12 Port Mirroring Support 3.13 IEEE 802.1Q VLAN Support 3.14 QoS Priority Support 3.15 Rate-Limiting Support 3.16 MAC Address Filtering Function 3.17 Queue Management Unit (QMU) 3.18 Device Clocks 3.19 Power 3.20 Internal Low Voltage LDO Regulator 3.21 Power Management 3.22 Wake-On-LAN 3.23 Interfaces 4.0 Register Descriptions 4.1 Device Registers 4.2 Register Map of CPU Accessible I/O Registers 4.3 Register Bit Definitions 4.4 Type-of-Service (TOS) Priority Control Registers 4.5 Indirect Access Data Registers 4.6 Power Management Control and Wake-Up Event Status 4.7 Go Sleep Time and Clock Tree Power-Down Control Registers 4.8 PHY and MII Basic Control Registers 4.9 Port 1 Control Registers 4.10 Port 2 Control Registers 4.11 Port 3 Control Registers 4.12 Switch Global Control Registers 4.13 Source Address Filtering Registers 4.14 TXQ Rate Control Registers 4.15 Auto-Negotiation Next Page Registers 4.16 EEE and Link Partner Advertisement Registers 4.17 Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 - 0x1FF) 4.18 Host MAC Address Registers: MARL, MARM, and MARH 4.19 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) 4.20 Internal I/O Register Space Mapping for Interrupt Registers (0x190 - 0x193) 4.21 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x19C - 0x1B9) 4.22 Management Information Base (MIB) Counters 4.23 Static MAC Address Table 4.24 Dynamic MAC Address Table 4.25 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read / Write Timing 7.2 Auto-Negotiation Timing 7.3 Serial EEPROM Interface Timing 7.4 Reset Timing and Power Sequencing 7.5 Reset Circuit Guidelines 7.6 Reference Circuits – LED Strap-In Pins 7.7 Reference Clock – Connection and Selection 8.0 Selection of Isolation Transformers 9.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
