Datasheet KSZ8862-16M, KSZ8862-32M (Microchip)

ОписаниеTwo-Port Ethernet Switch with Non-PCI Interface and Fiber Support
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KSZ8862-16M/-32M. Two-Port Ethernet Switch with Non-PCI Interface and. Fiber Support. Features

Datasheet KSZ8862-16M, KSZ8862-32M Microchip

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KSZ8862-16M/-32M Two-Port Ethernet Switch with Non-PCI Interface and Fiber Support Features QoS/CoS Packets Prioritization Support Switch Management
• Per Port, 802.1p and DiffServ-Based • Non-Blocking Switch Fabric Assures Fast Packet • Remapping of 802.1p Priority Field on a Per Port Delivery by Utilizing a 1K Entry Forwarding Table Basis and a Store-and-Forward Architecture
Power Modes, Packaging, and Power Supplies
• Fully Compliant with IEEE 802.3u Standards • Full-Chip Hardware Power-Down (Register Con- • Full-Duplex IEEE 802.3x Flow Control (Pause) figuration not Saved) Allows Low Power Dissipa- with Force Mode Option tion • Half-Duplex Back Pressure Flow Control • Per Port-Based, Software Power-Save on PHY
Advanced Switch Management
(Idle Link Detection, Register Configuration Pre- served) • IEEE 802.1Q VLAN Support for Up to 16 Groups (Full Range of VLAN IDs) • Single Power Supply: 3.3V • VLAN ID Tag/Untag Options, on a Per Port Basis • Commercial Temperature Range: 0°C to +70°C • IEEE 802.1p/Q Tag Insertion or Removal on a Per • Available in 128-Pin PQFP Port Basis (Egress) • Available in -16 Version for 8/16-Bit Bus Support • Programmable Rate Limiting at the Ingress and and -32 version for 32-Bit Bus Support Egress Ports
Additional Features
• Broadcast Storm Protection In Addition to Offering All of the Features of an Inte- • IEEE 802.1d Spanning Tree Protocol Support grated Layer-2 Managed Switch, the KSZ8862M • MAC Filtering Function to Filter or Forward Offers: Unknown Unicast Packets • Dynamic Buffer Memory Scheme • Direct Forwarding Mode Enabling the Processor - Essential for Applications Such as Video over to Identify the Ingress Port and to Specify the IP where Image Jitter is Unacceptable Egress Port • 2-Port Switch with a Flexible 8-Bit, 16-Bit, or 32- • Internet Group Management Protocol (IGMP) v1/ Bit Generic Host Processor Interfaces v2 Snooping Support for Multicast Packet Filtering • Microchip LinkMD® Cable Diagnostic to Deter- • IPV6 Multicast Listener Discovery (MLD) Snoop- mine Cable Length, Diagnose Faulty Cables, and ing Support Determine Distance to Fault
Fiber Support
• Hewlett Packard (HP) Auto-MDIX Crossover with • Integrated LED Driver and Post Amplifier for Disable and Enable Options 10BASE-FL and 100BASE-SX Optical Modules • Four Priority Queues to Handle Voice, Video, • 100BASE-FX/SX and 10BASE-FL Fiber Support Data, and Control Packets on Port 1 • Ability to Transmit and Receive Frames up to 1916 bytes
• Port Mirroring/Monitoring/Sniffing: Ingress and/or Egress Traffic to Any Port • MIB Counters for Fully Compliant Statistics Gath- ering - 34 MIB Counters Per Port • Loopback Modes for Remote Failure Diagnostics
Comprehensive Register Access
• Control Registers Configurable On-the-Fly (Port- Priority, 802.1p/d/Q)  2020 Microchip Technology Inc.

DS00003324A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 Auto-Negotiation Timing 7.10 Reset Timing 7.11 EEPROM Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service