Datasheet KSZ8862-16M, KSZ8862-32M (Microchip) - 3

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DS00003324A-page 3 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 Auto-Negotiation Timing 7.10 Reset Timing 7.11 EEPROM Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service