KSZ8862-16M/-32MTABLE 2-1:SIGNALSPinPin NameTypeDescriptionNumber Test Enable 1 TEST_EN I For normal operation, 1 kΩ pull-down this pin to ground. Scan Test Scan Mux Enable 2 SCAN_EN I For normal operation, 1 kΩ pull-down this pin to ground. Port 1 LED Indicators, defined as follows Switch Global Control Register 5: SGCR5 bit [15,9] [0, 0] Default[0, 1] P1LED3/P2LED3 — — P1LED2/P2LED2 Link/Activity 100Link/Activity P1LED1/P2LED1 Full-Duplex/Col 10Link/Activity 3 P1LED2 P1LED0/P2LED0 Speed Full-Duplex 4 P1LED1 5 P1LED0 OPU 6 P2LED2 Reg. SGCR5 bit [15,9] 7 P2LED1 [1, 0][1, 1] 8 P2LED0 P1LED3/P2LED3 Activity — P1LED2/P2LED2 Link — P1LED1/P2LED1 Full-Duplex/Col — P1LED0/P2LED0 Speed — Note: Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/ Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half- duplex); Speed = On (100BASE-T); Off (10BASE-T) Note: P1LED3 is pin 27. P2LED3 is pin 22. 9 DGND GND Digital ground. 3.3V digital V 10 VDDIO P DDIO input power supply for IO with well decoupling capaci- tors. Ready Return Not: For VLBus-like mode: Asserted by the host to complete synchronous 11 RDYRTNN IPD read cycles. If the host doesn’t connect to this pin, assert this pin. For burst mode (32-bit interface only): Host drives this pin low to signal waiting states. Bus Interface Clock Local bus clock for synchronous bus systems. Maximum frequency is 12 BCLK IPD 50 MHz. This pin should be tied Low or unconnected if it is in asynchronous mode. 13 NC IPU No connect. 14 NC OPU No connect. Synchronous Ready Not Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend accesses. 15 SRDYN OPU For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8862M drives this pin low to signal wait states. Interrupt 16 INTRN OPD Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4.7 kΩ pull-up resistor. 2020 Microchip Technology Inc.
DS00003324A-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 Auto-Negotiation Timing 7.10 Reset Timing 7.11 EEPROM Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
