link to page 5 link to page 96 KSZ8864CNX/RMNUB1.0INTRODUCTION1.1General Description The KSZ8864CNX/RMNUB is a highly-integrated, Layer 2-managed 4-port switch with optimized design, plentiful fea- tures and smallest package size. It is designed for cost-sensitive 10/100 Mbps 4-port switch systems with on-chip ter- mination, lowest-power consumption, and small package to save system cost. It has 1.4 Gbps high-performance memory bandwidth, shared memory-based switch fabric with full non-blocking configuration. It also provides an exten- sive feature set such as the power management, programmable rate limiting and priority ratio, tag/port-based VLAN, packet filtering, quality-of-service (QoS), four queue prioritization, management interface, MIB counters. Port 3 and Port 4 support either MII or RMII interfaces with SW3-MII/RMII and SW4-MII/RMII (see Figure 1-1) for KSZ8864CNX/ RMNUB data interface. An industrial temperature-grade version of the KSZ8864CNXIA and a qualified AEC-Q100 Auto- motive version of the KSZ8864RMNUB are also available (see Section “Product Identification System” ).The KSZ8864CNX/RMNUB provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KSZ8864CNX/RMNUB consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technol- ogy, media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8864CNX/RMNUB contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of the PHYs can be accessed through the MDC/MDIO interface. EEPROM can set all control registers by I2C controller inter- face for the unmanaged mode. The KSZ8864CNX/RMNUB adds Microchip's LinkMD® feature and is completely pin-compatible with the KSZ8864RMN device. FIGURE 1-1:FUNCTIONAL DIAGRAMKSZ8864CNX/RMNUB FIFO, FLOW CONTROL, VLAN LOOK UP ENGINE 10/100 10/100 AUTO MDI/MDIX T/TX MAC 1 QUEUE PHY1 MANAGEMENT 10/100 10/100 AUTO MDI/MDIX T/TX MAC 2 PHY2 BUFFER MANAGEMENT PORT 3 MAC 3 10/100 SW3-MII/RMII MAC 3 FRAME PORT 4 MAC 4 T BUFFERS 10/100 AGGING, PRIORITY SW4-MII/RMII MAC 4 MDC/MDIO MIB SMI, MIIM COUNTERS CONTROL REG SPI SPI P1LED[1:0] EEPROM LED I/F CONTROL INTERFACE P2LED[1:0] REGISTERS 2018 Microchip Technology Inc.
DS00002229D-page 5 Document Outline Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces 1.0 Introduction 1.1 General Description FIGURE 1-1: Functional Diagram 2.0 Pin Description and Configuration FIGURE 2-1: 64-QFN Pin Assignment (TOP View) TABLE 2-1: Signals - KSZ8864CNX/RMNUB TABLE 2-2: Strap-In Options - KSZ8864CNX/RMNUB 3.0 Functional Description 3.1 Physical Layer Transceiver 3.1.1 100BASE-TX Transmit 3.1.2 100BASE-TX Receive 3.1.3 PLL Clock Synthesizer 3.1.4 Scrambler/De-Scrambler (100BASE-TX Only) 3.1.5 10BASE-T Transmit 3.1.6 10BASE-T Receive 3.1.7 MDI/MDI-X Auto Crossover TABLE 3-1: MDI/MDI-X Pin Definitions FIGURE 3-1: Typical Straight Cable Connection FIGURE 3-2: Typical Crossover Cable Connection 3.1.8 Auto-Negotiation FIGURE 3-3: Auto-Negotiation Flow Chart 3.1.9 LinkMD® Cable Diagnostics 3.1.10 On-Chip Termination Resistors 3.2 Power Management TABLE 3-2: Internal Function Block Status 3.2.1 Normal Operation Mode 3.2.2 Energy Detect Mode 3.2.3 Soft Power-Down Mode 3.2.4 Power-Saving Mode 3.2.5 Port-Based Power-Down Mode 3.3 Switch Core 3.3.1 Address Look-Up 3.3.2 Learning 3.3.3 Migration 3.3.4 Aging 3.3.5 Forwarding 3.3.6 Switching Engine 3.3.7 Media Access Control (MAC) Operation 3.3.8 Inter-Packet Gap (IPG) 3.3.9 Back-Off Algorithm 3.3.10 Late Collision 3.3.11 Illegal Frames 3.3.12 Flow Control FIGURE 3-4: Destination Address Look-Up Flow Chart - Stage 1 FIGURE 3-5: Destination Address Resolution Flow Chart - Stage 2 3.3.13 Half-Duplex Back Pressure 3.3.14 Broadcast Storm Protection 3.3.15 MII Interface Operation 3.3.16 Switch MAC3/MAC4 SW3/SW4-MII Interface TABLE 3-3: Switch MAC3 SW3-MII and Mac4 SW4-MII Signals 3.3.17 Switch MAC3/MAC4 SW3/SW4-RMII Interface TABLE 3-4: MAC3 SW3-RMII and MAC4 SW4-RMII Connections 3.4 Advanced Functionality 3.4.1 QoS Priority Support FIGURE 3-6: 802.1p Priority Field Format 3.4.2 Spanning Tree Support 3.4.3 Rapid Spanning Tree Support 3.4.4 Tail Tagging Mode FIGURE 3-7: Tail Tag Frame Format TABLE 3-5: Tail Tag Rules 3.4.5 IGMP Support 3.4.6 Port Mirroring Support 3.4.7 VLAN Support TABLE 3-6: FID+DA Look Up in VLAN Mode TABLE 3-7: FID+SA Look Up in VLAN Mode 3.4.8 Rate Limiting Support 3.4.9 Ingress Rate Limit 3.4.10 Egress Rate Limit 3.4.11 Transmit Queue Ratio Programming 3.4.12 Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast 3.4.13 Configuration Interface FIGURE 3-8: EEPROM Configuration Timing Diagram 3.4.14 SPI Slave Serial Bus Configuration TABLE 3-8: SPI Connections FIGURE 3-9: SPI Write Data Cycle FIGURE 3-10: SPI Read Data Cycle FIGURE 3-11: SPI Multiple Write FIGURE 3-12: SPI Multiple Read 3.5 MII Management (MIIM) Interface TABLE 3-9: MII Management Frame Format 3.6 Serial Management Interface (SMI) TABLE 3-10: Serial Management Interface (SMI) Frame Format 4.0 Register Descriptions TABLE 4-1: Registers Descriptions 4.1 Global Registers TABLE 4-2: Global Register Descriptions 4.2 Port Registers TABLE 4-3: Port Registers 4.3 Advanced Control Registers TABLE 4-4: Advanced Control Register Descriptions TABLE 4-5: Data Rate Selection in 100BT TABLE 4-6: Data Rate Selection in 10BT 4.4 Static MAC Address Table TABLE 4-7: Format of Static MAC Table for Reads TABLE 4-8: Format of Static MAC Table for Writes 4.5 VLAN Table TABLE 4-9: VLAN Table TABLE 4-10: VLAN ID and Indirect Registers 4.6 Dynamic MAC Address Table TABLE 4-11: Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters TABLE 4-12: MIB Counters 4.8 MIIM Registers TABLE 4-13: MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics TABLE 6-1: Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing FIGURE 7-1: EEPROM Interface Input Receive Timing Diagram FIGURE 7-2: EEPROM Interface Output Transmit Timing Diagram TABLE 7-1: EEPROM Timing Parameters 7.2 MII Timing FIGURE 7-3: MAC Mode MII Timing - Data Received from MII FIGURE 7-4: MAC Mode MII TIming - Data Transmitted from MII TABLE 7-2: MAC Mode MII Timing Parameters FIGURE 7-5: PHY Mode MII Timing - Data Received from MII FIGURE 7-6: PHY Mode MII Timing - Data Transmitted from MII TABLE 7-3: PHY Mode MII Timing Parameters 7.3 RMII Timing FIGURE 7-7: RMII Timing - Data Received from RMII FIGURE 7-8: RMII Timing - Data Transmitted to RMII TABLE 7-4: RMII Timing Parameters 7.4 SPI Timing FIGURE 7-9: SPI Input TiminG FIGURE 7-10: SPI OUTput Timing TABLE 7-5: SPI Timing Parameters 7.5 Auto-Negotiation Timing FIGURE 7-11: Auto-Negotiation Timing TABLE 7-6: Auto-Negotiation Timing Parameters 7.6 MDC/MDIO Timing FIGURE 7-12: MDC/MDIO Timing TABLE 7-7: MDC/MDIO Typical Timing Parameters 7.7 Reset Timing FIGURE 7-13: Reset Timing Diagram TABLE 7-8: Reset Timing Parameters 8.0 Reset Circuit FIGURE 8-1: Recommended Reset Circuit FIGURE 8-2: Recommended Reset Circuit for CPU/FPGA Reset Output 9.0 Selection of Isolation Transformer, (Note 1) TABLE 9-1: Transformer Selection Criteria 9.0.1 Selection of Transformer Vendors TABLE 9-2: Qualified Magnetic Vendors 9.0.2 Selection of Reference Crystal TABLE 9-3: Typical Reference Crystal Characteristics 10.0 Package Outline FIGURE 10-1: 64-Lead QFN 8 mm x 8 mm Package The Microchip WebSite Customer Change Notification Service Customer Support Appendix A: Data Sheet Revision history Product Identification System AMERICAS Corporate Office Atlanta Austin, TX Boston Chicago Dallas Detroit Houston, TX Indianapolis Los Angeles Raleigh, NC New York, NY San Jose, CA Canada - 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