KSZ8864CNX/RMNUBTABLE 2-1:SIGNALS - KSZ8864CNX/RMNUB (CONTINUED)Type,PinPinNotePortPin Function, Note 2NumberName1 LED indicator for Port 2 49 P2LED1 IPU/O 2 This pin has to be pulled down by a 1 kΩ resistor in the design for KSZ8864CNX/RMNUB. LED indicator for Port 2 Strap option: Switch MAC3 used only 50 P2LED0 IPU/O 2 PU (default) = Select MII interface for the Switch MAC3 SW3-MII PD = Select RMII interface for the Switch MAC3 SW3-RMII LED indicator for Port 1 Strap option: Switch RMII used only PU (default) = Select the device as Clock mode, when use RMII interface, all clock source come from pin x1/x2 crystal 25 MHz. PD = Select the device as normal mode when use RMII interface. 51 P1LED1 IPU/O 1 All clock sources come from SW4-RMII SM4TXC pin with an exter- nal input 50 MHz clock. In the normal mode, the 25 MHz crystal clock from pin X1/X2 does not take affect and should disable SW4- RMII SW4RXC 50 MHz clock output by the register 87. The normal mode is used when SW4-RMII receives an external 50 MHz RMII reference clock from pin SM4TXC. LED indicator for Port 1 Strap option: for Switch MAC4 only 52 P1LED0 IPU/O 1 PU (default) = Select MII interface for the Switch MAC4 SW4-MII PD = Select RMII interface for the Switch MAC4 SW4-RMII 53 MDC IPU All MII management interface clock, Or SMI interface clock. MII management data I/O, Or SMI interface data I/O. 54 MDIO IPU/O All Note : Need an external pull-up when driven. SPI serial data output in SPI Slave mode 55 SPIQ IPU/O All Note : Need an external pull-up when driven. (1) Input clock up to 25 MHz in SPI Slave mode, 56 SPIC/SCL IPU/O All (2) Output clock at 61 kHz in I2C Master mode Note : Need an external pull-up when driven. (1) Serial data input in SPI slave mode; 57 SPID/SDA IPU/O All (2) Serial data input/output in I2C master mode Note : Need an external pull-up when driven. Active-low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, 58 SPIS_N IPU All the device is deselected and SPIQ is held in high-impedance state, a high-to-low transition to initiate the SPI data transfer. (2) Not used in I2C Master mode. DS00002229D-page 10
2018 Microchip Technology Inc. Document Outline Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces 1.0 Introduction 1.1 General Description FIGURE 1-1: Functional Diagram 2.0 Pin Description and Configuration FIGURE 2-1: 64-QFN Pin Assignment (TOP View) TABLE 2-1: Signals - KSZ8864CNX/RMNUB TABLE 2-2: Strap-In Options - KSZ8864CNX/RMNUB 3.0 Functional Description 3.1 Physical Layer Transceiver 3.1.1 100BASE-TX Transmit 3.1.2 100BASE-TX Receive 3.1.3 PLL Clock Synthesizer 3.1.4 Scrambler/De-Scrambler (100BASE-TX Only) 3.1.5 10BASE-T Transmit 3.1.6 10BASE-T Receive 3.1.7 MDI/MDI-X Auto Crossover TABLE 3-1: MDI/MDI-X Pin Definitions FIGURE 3-1: Typical Straight Cable Connection FIGURE 3-2: Typical Crossover Cable Connection 3.1.8 Auto-Negotiation FIGURE 3-3: Auto-Negotiation Flow Chart 3.1.9 LinkMD® Cable Diagnostics 3.1.10 On-Chip Termination Resistors 3.2 Power Management TABLE 3-2: Internal Function Block Status 3.2.1 Normal Operation Mode 3.2.2 Energy Detect Mode 3.2.3 Soft Power-Down Mode 3.2.4 Power-Saving Mode 3.2.5 Port-Based Power-Down Mode 3.3 Switch Core 3.3.1 Address Look-Up 3.3.2 Learning 3.3.3 Migration 3.3.4 Aging 3.3.5 Forwarding 3.3.6 Switching Engine 3.3.7 Media Access Control (MAC) Operation 3.3.8 Inter-Packet Gap (IPG) 3.3.9 Back-Off Algorithm 3.3.10 Late Collision 3.3.11 Illegal Frames 3.3.12 Flow Control FIGURE 3-4: Destination Address Look-Up Flow Chart - Stage 1 FIGURE 3-5: Destination Address Resolution Flow Chart - Stage 2 3.3.13 Half-Duplex Back Pressure 3.3.14 Broadcast Storm Protection 3.3.15 MII Interface Operation 3.3.16 Switch MAC3/MAC4 SW3/SW4-MII Interface TABLE 3-3: Switch MAC3 SW3-MII and Mac4 SW4-MII Signals 3.3.17 Switch MAC3/MAC4 SW3/SW4-RMII Interface TABLE 3-4: MAC3 SW3-RMII and MAC4 SW4-RMII Connections 3.4 Advanced Functionality 3.4.1 QoS Priority Support FIGURE 3-6: 802.1p Priority Field Format 3.4.2 Spanning Tree Support 3.4.3 Rapid Spanning Tree Support 3.4.4 Tail Tagging Mode FIGURE 3-7: Tail Tag Frame Format TABLE 3-5: Tail Tag Rules 3.4.5 IGMP Support 3.4.6 Port Mirroring Support 3.4.7 VLAN Support TABLE 3-6: FID+DA Look Up in VLAN Mode TABLE 3-7: FID+SA Look Up in VLAN Mode 3.4.8 Rate Limiting Support 3.4.9 Ingress Rate Limit 3.4.10 Egress Rate Limit 3.4.11 Transmit Queue Ratio Programming 3.4.12 Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast 3.4.13 Configuration Interface FIGURE 3-8: EEPROM Configuration Timing Diagram 3.4.14 SPI Slave Serial Bus Configuration TABLE 3-8: SPI Connections FIGURE 3-9: SPI Write Data Cycle FIGURE 3-10: SPI Read Data Cycle FIGURE 3-11: SPI Multiple Write FIGURE 3-12: SPI Multiple Read 3.5 MII Management (MIIM) Interface TABLE 3-9: MII Management Frame Format 3.6 Serial Management Interface (SMI) TABLE 3-10: Serial Management Interface (SMI) Frame Format 4.0 Register Descriptions TABLE 4-1: Registers Descriptions 4.1 Global Registers TABLE 4-2: Global Register Descriptions 4.2 Port Registers TABLE 4-3: Port Registers 4.3 Advanced Control Registers TABLE 4-4: Advanced Control Register Descriptions TABLE 4-5: Data Rate Selection in 100BT TABLE 4-6: Data Rate Selection in 10BT 4.4 Static MAC Address Table TABLE 4-7: Format of Static MAC Table for Reads TABLE 4-8: Format of Static MAC Table for Writes 4.5 VLAN Table TABLE 4-9: VLAN Table TABLE 4-10: VLAN ID and Indirect Registers 4.6 Dynamic MAC Address Table TABLE 4-11: Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters TABLE 4-12: MIB Counters 4.8 MIIM Registers TABLE 4-13: MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics TABLE 6-1: Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing FIGURE 7-1: EEPROM Interface Input Receive Timing Diagram FIGURE 7-2: EEPROM Interface Output Transmit Timing Diagram TABLE 7-1: EEPROM Timing Parameters 7.2 MII Timing FIGURE 7-3: MAC Mode MII Timing - Data Received from MII FIGURE 7-4: MAC Mode MII TIming - Data Transmitted from MII TABLE 7-2: MAC Mode MII Timing Parameters FIGURE 7-5: PHY Mode MII Timing - Data Received from MII FIGURE 7-6: PHY Mode MII Timing - Data Transmitted from MII TABLE 7-3: PHY Mode MII Timing Parameters 7.3 RMII Timing FIGURE 7-7: RMII Timing - Data Received from RMII FIGURE 7-8: RMII Timing - Data Transmitted to RMII TABLE 7-4: RMII Timing Parameters 7.4 SPI Timing FIGURE 7-9: SPI Input TiminG FIGURE 7-10: SPI OUTput Timing TABLE 7-5: SPI Timing Parameters 7.5 Auto-Negotiation Timing FIGURE 7-11: Auto-Negotiation Timing TABLE 7-6: Auto-Negotiation Timing Parameters 7.6 MDC/MDIO Timing FIGURE 7-12: MDC/MDIO Timing TABLE 7-7: MDC/MDIO Typical Timing Parameters 7.7 Reset Timing FIGURE 7-13: Reset Timing Diagram TABLE 7-8: Reset Timing Parameters 8.0 Reset Circuit FIGURE 8-1: Recommended Reset Circuit FIGURE 8-2: Recommended Reset Circuit for CPU/FPGA Reset Output 9.0 Selection of Isolation Transformer, (Note 1) TABLE 9-1: Transformer Selection Criteria 9.0.1 Selection of Transformer Vendors TABLE 9-2: Qualified Magnetic Vendors 9.0.2 Selection of Reference Crystal TABLE 9-3: Typical Reference Crystal Characteristics 10.0 Package Outline FIGURE 10-1: 64-Lead QFN 8 mm x 8 mm Package The Microchip WebSite Customer Change Notification Service Customer Support Appendix A: Data Sheet Revision history Product Identification System AMERICAS Corporate Office Atlanta Austin, TX Boston Chicago Dallas Detroit Houston, TX Indianapolis Los Angeles Raleigh, NC New York, NY San Jose, CA Canada - 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