Datasheet KSZ8893FQL (Microchip) - 9

KSZ8893FQL TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1
KSZ8893FQL operating modes (defined below):
(MCHS, MCCS) Description
9 MCHS IPD (0, 0) Normal 3 port switch mode (3 MAC + 2 PHY) MC mode is disabled. Port 1 is either Fiber or UTP. Port 2 is UTP. Port 3 (MII) is enabled. (0, 1) Center MC mode (3 MAC + 2 PHY) MC mode is enabled. Port 1 is Fiber and has Center MC enabled. Port 2 is UTP. Port 3 (MII) is enabled. (1, 0) Terminal MC mode (2 MAC + 2 PHY) MC mode is enabled. 10 MCCS IPD Port 1 is Fiber and has Terminal MC enabled. Port 2 is UTP. Port 3 (MII) is disabled. (1, 1) Terminal MC mode (3 MAC + 2 PHY) MC mode is enabled. Port 1 Fiber and has Terminal MC enabled. Port 2 is UTP. Port 3 (MII) is enabled. Power Down Detect 1 = Normal operation. 0 = Power down detected. 11 PDD# IPU In Terminal MC mode (pin MCHS is ‘1’), a high to low transition to this pin will cause port 1 (fiber) to generate and send out an “Indicate Terminal MC Condi- tion” OAM frame with the S0 status bit set to ‘1’. 1 = Advertise the switch’s flow control capability via auto-negotiation. 12 ADVFC IPU 0 = Will not advertise the switch’s flow control capability via auto-negotiation. 1 = Enable auto-negotiation on port 2. 13 P2ANEN IPU 0 = Disable auto-negotiation on port 2. 1 = Force port 2 to 100BT if P2ANEN = 0. 14 P2SPD IPD 0 = Force port 2 to 10BT if P2ANEN = 0. 1 = Port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in full duplex mode if P2ANEN = 0. 15 P2DPX IPD 0 = Port 2 default to half duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in half duplex mode if P2ANEN = 0. 1 = Always enable (force) port 2 flow control feature. 16 P2FFC IPD 0 = Port 2 flow control feature enable is determine by the auto-negotiation result. 1 = Normal function. 17 P1FST OPU 0 = MC in loopback mode or MC abnormal conditions occur.  2019 Microchip Technology Inc. DS00003038B-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Media Conversion 3.2 Physical Layer Transceiver 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Unicast MAC Address Filtering 3.6 Configuration Interface 3.7 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-141) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service