Datasheet KSZ8895MLUB (Microchip) - 9

KSZ8895MLUB TABLE 2-1: SIGNALS - KSZ8895MLUB (CONTINUED) Type, Pin Pin Note Port Pin Function Number Name 2-1
60 PMRXC I/O 5 Reserved for MLUB. No connect. 61 PMRXDV IPD/O 5 Reserved for MLUB. No connect. Reserved for MLUB. Strap option: 62 PMRXD3 IPD/O 5 PD (default) = enable flow control. PU = disable flow control. Reserved for MLUB. Strap option: 63 PMRXD2 IPD/O 5 PD (default) = disable back pressure. PU = enable back pressure. Reserved for MLUB. Strap option: 64 PMRXD1 IPD/O 5 PD (default) = drop excessive collision packets. PU = does not drop excessive collision packets. Reserved for MLUB. Strap option: 65 PMRXD0 IPD/O 5 PD (default) = disable aggressive back-off algorithm in half-duplex mode. PU = enable for performance enhancement. Reserved for MLUB. Strap option: 66 PMRXER IPD/O 5 PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. Reserved for MLUB. Strap option for port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or 67 PCRS IPD/O 5 fails. PU = force full-duplex if auto-negotiation is disabled or fails. Refer to Register 76. Reserved for MLUB. Strap option for port 4 only. 68 PCOL IPD/O 5 PD (default) = no force flow control, normal operation. PU = force flow control. Refer to Register 66. 69 SMTXEN IPD — Port 5 Switch MII transmit enable. 70 SMTXD3 IPD — Port 5 Switch MII transmit bit 3. 71 SMTXD2 IPD — Port 5 Switch MII transmit bit 2. 72 SMTXD1 IPD — Port 5 Switch MII transmit bit 1. 73 SMTXD0 IPD — Port 5 Switch MII transmit bit 0. 74 SMTXER IPD — Port 5 Switch MII transmit error Port 5 Switch MII transmit clock: 75 SMTXC I/O — Input: SW5-MII MAC mode. Output: SW5-MII PHY mode.  2018 Microchip Technology Inc. DS00002680A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 SPI Timing 7.5 Auto-Negotiation Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service