KSZ8993MTABLE 2-1:SIGNALS (CONTINUED)PinPin NameTypeDescriptionNumber Priority select. Select queue servicing if using split queues. Use the table below to select the desired servicing. Note that this selection effects all split transmit queue ports in the same way. 88 SCONF1 IPD [SCONF1, SCONF0]Description 89 SCONF0 [0,0] Disable, outputs tri-stated [0,1] PHY mode MII [1,0] MAC mode MII [1,1] PHY mode SNI 90 DGND GND Digital ground 91 VDDC P 1.8V digital VDD Priority select. Select queue servicing if using split queues. Use the table below to select the desired servicing. Note that this selection effects all split transmit queue ports in the same way. [PRSEL1, PRSEL0]Description 92 PRSEL1 [0,0] Transmit all high priority before low priority IPD 93 PRSEL0 Transmit high priority and low priority at 10:1 [0,1] ratio Transmit high priority and low priority at 5:1 [1,0] ratio Transmit high priority and low priority at [1,1] 2:1 ratio 94 MDC IPU MII management interface: Clock input MII management interface: Data input/output 95 MDIO IPU/O Note: an external 4.7 kΩ pull-up is needed on this pin when it is in use. SPI slave mode: Serial data output 96 SPIQ OPU See description for pins 100 and 101. SPI slave mode/I2C slave mode: Clock input 97 SCL IPU/O I2C master mode: clock output See description for pins 100 and 101. SPI slave mode: Serial data input 98 SDA IPU/O I2C master/slave mode: Serial data input/output See description for pins 100 and 101. SPI slave mode: Chip select (active-low) When SPIS_N is high, the KSZ8993M is deselected and SPIQ is held in 99 SPIS_N IPU high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description for pins 100 and 101. DS00003066A-page 10
2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
