Datasheet KSZ9477S (Microchip)

Описание7-Port Gigabit Ethernet Switch with Ring Redundancy, SGMII and RGMII/MII/RMII Interfaces
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KSZ9477S. 7-Port Gigabit Ethernet Switch with Ring Redundancy,. SGMII and RGMII/MII/RMII Interfaces. Highlights

Datasheet KSZ9477S Microchip

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MICROCHIP - KSZ9477STXI-TR - Ethernet контроллер, 1 Гбит/с, IEEE 802.3, IEEE 802.3u, IEEE 802.3ab, 1.14 В, 1.26 В, TQFP
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KSZ9477S 7-Port Gigabit Ethernet Switch with Ring Redundancy, SGMII and RGMII/MII/RMII Interfaces Highlights
• Five Integrated PHY Ports - 1000BASE-T/100BASE-TX/10BASE-Te IEEE 802.3 • One port with 10/100/1000 Ethernet MAC - Fast Link-up option significantly reduces link-up time and SGMII interface - Auto-negotiation and Auto-MDI/MDI-X support • One port with 10/100/1000 Ethernet MAC - On-chip termination resistors and internal biasing for and configurable RGMII/MII/RMII interface differential pairs to reduce power • EtherSynch® with ful support for IEEE 1588v2 - LinkMD® cable diagnostic capabilities Precision Time Protocol (PTP) • Advanced Switch Capabilities • IEEE 802.1AS/Qav Audio Video Bridging (AVB) - IEEE 802.1Q VLAN support for 128 active VLAN • IEEE 802.1X access control support groups and the full range of 4096 VLAN IDs • Five ports with integrated 10/100/1000BASE-T PHY - IEEE 802.1p/Q tag insertion/removal on per port basis transceivers w/ optional Quiet-WIRE® EMC filtering - VLAN ID on per port or VLAN basis • Non-blocking wire-speed Ethernet switching fabric - IEEE 802.3x full-duplex flow control and half-duplex back pressure collision control • Full-featured forwarding and filtering control, includ- - IEEE 802.1X access control (Port and MAC address) ing Access Control List (ACL) filtering - IGMP v1/v2/v3 snooping for multicast packet filtering • Full VLAN and QoS support - IPv6 multicast listener discovery (MLD) snooping • EtherGreen™ power management features, - IPv4/IPv6 QoS support, QoS/CoS packet prioritization including low power standby - 802.1p QoS packet classification with 4 priority queues • Flexible management interface options: SPI, I2C, - Programmable rate limiting at ingress/egress ports MIIM, and in-band management via any port • Ring Redundancy • Industrial temperature range support - DLR (EtherNet/IP) support • 128-pin TQFP-EP (14 x 14mm) RoHS compliant pkg - HSR (IEC 62439-3) support • IEEE 1588v2 PTP and Clock Synchronization
Target Applications
- Transparent Clock (TC) with auto correction update - Master and slave Ordinary Clock (OC) support • Industrial Ethernet (Profinet, MODBUS, Ethernet/IP) - End-to-end (E2E) or peer-to-peer (P2P) • Real-time Ethernet networks - PTP multicast and unicast message support • IEC 61850 networks w/ power substation automation - PTP message transport over IPv4/v6 and IEEE 802.3 • Industrial control/automation switches - IEEE 1588v2 PTP packet filtering • Networked measurement and control systems - Synchronous Ethernet support via recovered clock • Test and measurement equipment • Audio Video Bridging (AVB) - Compliant with IEEE 802.1BA/AS/Qat/Qav standards
- Priority queuing, Low latency cut-through mode • Switch Management Capabilities - gPTP time synchronization, credit-based traffic shaper - Time aware traffic scheduler per port - 10/100/1000Mbps Ethernet switch basic functions: frame buffer management, address look-up table, • Comprehensive Configuration Registers Access queue management, MIB counters - High-speed 4-wire SPI (up to 50MHz), I2C interfaces - Non-blocking store-and-forward switch fabric assures provide access to all internal registers fast packet delivery by utilizing 4096 entry forwarding - MII Management (MIIM, MDC/MDIO 2-wire) Interface table with 256kByte frame buffer provides access to all PHY registers - Jumbo packet support up to 9000 bytes - In-band management via any of the data ports - Port mirroring/monitoring/sniffing: - I/O pin strapping facility to set register bits at reset ingress and/or egress traffic to any port • Power Management - Rapid spanning tree protocol (RSTP) support for topol- - Energy detect power-down mode on cable disconnect ogy management and ring/linear recovery - Dynamic clock tree control - Multiple spanning tree protocol (MSTP) support - Unused ports can be individually powered down • One External MAC Port with SGMII - Full-chip software power-down • One External MAC Port with RGMII/MII/RMII - Wake-on-LAN (WoL) standby power mode - RGMII v2.0, RMII v1.2 with 50MHz reference clock input/output option, MII in PHY/MAC mode  2017-2019 Microchip Technology Inc. DS00002392C-page 1 Document Outline 1.0 Preface 1.1 Glossary of Terms TABLE 1-1: General Terms 1.2 Buffer Types TABLE 1-2: Buffer Types 1.3 Register Nomenclature TABLE 1-3: Register Nomenclature 1.4 References 2.0 Introduction 2.1 General Description FIGURE 2-1: Internal Block Diagram 3.0 Pin Descriptions and Configuration 3.1 Pin Assignments FIGURE 3-1: Pin Assignments (Top View) TABLE 3-1: Pin Assignments 3.2 Pin Descriptions TABLE 3-2: Pin Descriptions 3.2.1 Configuration Straps TABLE 3-3: Configuration Strap Descriptions 4.0 Functional Description 4.1 Physical Layer Transceiver (PHY) 4.1.1 1000BASE-T Transceiver 4.1.2 100BASE-TX Transceiver 4.1.3 10BASE-Te Transceiver 4.1.4 Auto MDI/MDI-X TABLE 4-1: MDI/MDI-X Pin Definitions 4.1.5 Pair-Swap, Alignment, and Polarity Check 4.1.6 Wave Shaping, Slew-Rate Control, and Partial Response 4.1.7 Auto-Negotiation FIGURE 4-1: Auto-Negotiation and Parallel Operation 4.1.8 Quiet-WIRE Filtering TABLE 4-2: Enabling and Disabling Quiet-WIRE 4.1.9 Fast Link-Up 4.1.10 LinkMD® Cable Diagnostics 4.1.11 LinkMD®+ Enhanced Diagnostics: Receive Signal Quality Indicator 4.1.12 Remote PHY Loopback FIGURE 4-2: Remote PHY Loopback 4.2 LEDs 4.2.1 Single-LED Mode TABLE 4-3: Single-LED Mode Pin Definition 4.2.2 Tri-Color Dual-LED Mode TABLE 4-4: Tri-Color Dual-LED Mode Pin Definition 4.3 Media Access Controller (MAC) 4.3.1 MAC Operation 4.3.2 Inter-Packet Gap (IPG) 4.3.3 Back-Off Algorithm 4.3.4 Late Collision 4.3.5 Legal Packet Size 4.3.6 Flow Control 4.3.7 Half-Duplex Back Pressure 4.3.8 Flow Control and Back Pressure Registers TABLE 4-5: Flow Control and back Pressure Registers 4.3.9 Broadcast Storm Protection 4.3.10 Self-Address Filtering 4.4 Switch 4.4.1 Switching Engine 4.4.2 Address Lookup TABLE 4-6: Address Lookup Table Hashing Options TABLE 4-7: Reserved Multicast Address Table FIGURE 4-3: Packet Forwarding Process Flowchart TABLE 4-8: Lookup Engine Registers 4.4.3 IEEE 802.1Q VLAN TABLE 4-9: VLAN Forwarding TABLE 4-10: Hashed(DA) + FID Lookup in VLAN Mode TABLE 4-11: Hashed(SA) + FID Lookup in VLAN Mode TABLE 4-12: VLAN Registers 4.4.4 Quality-of-Service (QoS) Priority Support FIGURE 4-4: 802.p Priority Field Format 4.4.5 Traffic Conditioning & Policing 4.4.6 Spanning Tree Support TABLE 4-13: Spanning Tree States 4.4.7 Rapid Spanning Tree Support 4.4.8 Multiple Spanning Tree Support 4.4.9 Tail Tagging Mode FIGURE 4-5: Tail Tag Frame Format TABLE 4-14: Receive Tail Tag Format (from Switch to Host) TABLE 4-15: Transmit Tail Tag Format (from Host to Switch) FIGURE 4-6: PTP Mode Tail Tag Frame Format 4.4.10 IGMP Support 4.4.11 IPv6 MLD Snooping 4.4.12 Port Mirroring 4.4.13 Scheduling and Rate Limiting 4.4.14 Egress Traffic Shaping 4.4.15 Low Latency Cut-Through Mode 4.4.16 Ingress MAC Address Filtering Function 4.4.17 802.1X Access Control 4.4.18 Access Control List (ACL) Filtering TABLE 4-16: ACL Processing Entry Parameters FIGURE 4-7: ACL Structure and Example Rule Values TABLE 4-17: Matching Rule Options TABLE 4-18: ACL Matching Rule Parameters for MD = 01 TABLE 4-19: ACL Matching Rule Parameters for MD = 10 TABLE 4-20: ACL Matching Rule Parameters for MD = 11 TABLE 4-21: ACL Action Rule Parameters for Non-count Modes (MD ≠ 01 or ENB ≠ 00) TABLE 4-22: ACL Action Rule Parameters for count Mode (MD = 01 or ENB = 00) FIGURE 4-8: ACL Table Format TABLE 4-23: ACL Registers 4.5 Ring Redundancy 4.5.1 Device Level Ring (DLR) 4.5.2 High Availability Seamless Redundancy (HSR) 4.6 IEEE 1588 Precision Time Protocol 4.6.1 IEEE 1588 PTP System Time Clock FIGURE 4-9: PTP System Clock Overview 4.6.2 IEEE 1588 PTP Messaging Processing 4.6.3 IEEE 1588 PTP Event Triggering and Timestamping 4.7 Audio Video Bridging and Time Sensitive Networks 4.8 NAND Tree Support TABLE 4-24: NAND Tree Test Pin Order 4.9 Clocking 4.9.1 Primary Clock 4.9.2 Port 6 RGMII/MII/RMII Clocks 4.9.3 Port 7 SGMII Clock 4.9.4 Serial Management Interface Clock 4.9.5 Synchronous Ethernet and SYNCLKO 4.10 Power FIGURE 4-10: Power Connection Diagram 4.11 Power Management TABLE 4-25: MDI/MDI-X Pin Definitions 4.11.1 Normal Operation Mode 4.11.2 Energy-Detect Mode 4.11.3 Global Soft Power-Down Mode 4.11.4 Port-Based Power Down 4.11.5 Wake on LAN (WoL) 4.12 Management Interface 4.12.1 SPI Slave Bus TABLE 4-26: Register Access using the SPI Interface FIGURE 4-11: SPI Register Read Operation FIGURE 4-12: SPI Register Write Operation 4.12.2 I2C Bus FIGURE 4-13: Single Byte Register Write FIGURE 4-14: Single Byte Register Read FIGURE 4-15: Burst Register Write FIGURE 4-16: Burst Register Read 4.12.3 MII Management (MIIM) Interface TABLE 4-27: MII Management Interface Frame Format TABLE 4-28: Standard MIIM Registers 4.13 In-Band Management FIGURE 4-17: In-Band Management Frame Format 4.14 MAC Interface (Ports 6 and 7) 4.14.1 Media Independent Interface (MII) (Port 6) TABLE 4-29: MII (PHY Mode) Connection to External MAC TABLE 4-30: MII (MAC Mode) Connection to External PHY 4.14.2 Reduced Media Independent Interface (RMII) (Port 6) TABLE 4-31: RMII Signal Descriptions TABLE 4-32: RMII Connection to External MAC TABLE 4-33: RMII Connection to External PHY 4.14.3 Reduced Gigabit Media Independent Interface (RGMII) (Port 6) TABLE 4-34: RGMII Signal Descriptions 4.14.4 Serial Gigabit Media Independent Interface (SGMII) (Port 7) 5.0 Device Registers FIGURE 5-1: Register Address Mapping FIGURE 5-2: Byte Ordering TABLE 5-1: Global Register Address Map TABLE 5-2: Port N (1-7) Register Address Map 5.1 Global Registers 5.1.1 Global Operation Control Registers (0x0000 - 0x00FF) 5.1.2 Global I/O Control Registers (0x0100 - 0x01FF) 5.1.3 Global PHY Control and Status Registers (0x0200 - 0x02FF) 5.1.4 Global Switch Control Registers (0x0300 - 0x03FF) 5.1.5 Global Switch Look Up Engine (LUE) Control Registers (0x0400 - 0x04FF) 5.1.6 Global Switch PTP Control Registers (0x0500 - 0x05FF) 5.1.7 Global Switch Ring Redundancy Control Registers (0x0600 - 0x06FF) 5.2 Port Registers 5.2.1 Port N: Port Operation Control Registers (0xN000 - 0xN0FF) 5.2.2 Port N: Port Ethernet PHY Registers (0xN100 - 0xN1FF) 5.2.3 Port N: Port SGMII Control Registers (0xN200 - 0xN2FF) 5.2.4 Port N: Port RGMII/MII/RMII Control Registers (0xN300 - 0xN3FF) 5.2.5 Port N: Port Switch MAC Control Registers (0xN400 - 0xN4FF) TABLE 5-3: Data Rate Selection Table for Ingress and Egress Rate Limiting 5.2.6 Port N: Port Switch MIB Counters Registers (0xN500 - 0xN5FF) 5.2.7 Port N: Port Switch ACL Control Registers (0xN600 - 0xN6FF) 5.2.8 Port N: Port Switch Ingress Control Registers (0xN800 - 0xN8FF) 5.2.9 Port N: Port Switch Egress Control Registers (0xN900 - 0xN9FF) 5.2.10 Port N: Port Switch Queue Management Control Registers (0xNA00 - 0xNAFF) 5.2.11 Port N: Port Switch Address Lookup Control Registers (0xNB00 - 0xNBFF) 5.2.12 Port N: Port Switch PTP Control Registers (0xNC00 - 0xNCFF) 5.3 Tables and MIB Counters (Access) 5.3.1 Address Lookup (ALU) Table FIGURE 5-3: Address Lookup Table Configuration 5.3.2 Static Address Table 5.3.3 Reserved Multicast Address Table 5.3.4 VLAN Table FIGURE 5-4: VLAN Table Structure TABLE 5-4: VLAN Table Data Fields 5.3.5 Access Control List (ACL) Table TABLE 5-5: ACL Field Register Mapping 5.3.6 Management Information Base (MIB) Counters TABLE 5-6: MIB Counters 5.4 MDIO Manageable Device (MMD) Registers (Indirect) TABLE 5-7: MMD Register Map 5.4.1 MMD Signal Quality Channel A Register 5.4.2 MMD Signal Quality Channel B Register 5.4.3 MMD Signal Quality Channel C Register 5.4.4 MMD Signal Quality Channel D Register 5.4.5 MMD LED Mode Register 5.4.6 MMD EEE Advertisement Register 5.4.7 MMD Quiet-WIRE Configuration 0 Register 5.4.8 MMD Quiet-WIRE Configuration 1 Register 5.4.9 MMD Quiet-WIRE Configuration 2 Register 5.4.10 MMD Quiet-WIRE Configuration 3 Register 5.4.11 MMD Quiet-WIRE Configuration 4 Register 5.4.12 MMD Quiet-WIRE Configuration 5 Register 5.4.13 MMD Quiet-WIRE Configuration 6 Register 5.4.14 MMD Quiet-WIRE Configuration 7 Register 5.4.15 MMD Quiet-WIRE Configuration 8 Register 5.4.16 MMD Quiet-WIRE Configuration 9 Register 5.4.17 MMD Quiet-WIRE Configuration 10 Register 5.4.18 MMD Quiet-WIRE Configuration 11 Register 5.4.19 MMD Quiet-WIRE Configuration 12 Register 5.4.20 MMD Quiet-WIRE Configuration 13 Register 5.4.21 MMD Quiet-WIRE Configuration 14 Register 5.4.22 MMD Quiet-WIRE Configuration 15 Register 5.5 SGMII Registers (Indirect) TABLE 5-8: SGMII Register Map (Indirect) 5.5.1 SGMII Control Register 5.5.2 SGMII Status Register 5.5.3 SGMII PHY ID 1 Register 5.5.4 SGMII PHY ID 2 Register 5.5.5 SGMII Auto-Negotiation Advertisement Register 5.5.6 SGMII Auto-Negotiation Link Partner Base Ability Register 5.5.7 SGMII Auto-Negotiation Expansion Register 5.5.8 SGMII Digital Control Register 5.5.9 SGMII Auto-Negotiation Control Register 5.5.10 SGMII Auto-Negotiation Status Register 6.0 Operational Characteristics 6.1 Absolute Maximum Ratings* 6.2 Operating Conditions** 6.3 Electrical Characteristics TABLE 6-1: Electrical Characteristics 6.4 Timing Specifications 6.4.1 RGMII Timing FIGURE 6-1: RGMII Timing TABLE 6-2: RGMII Timing Values 6.4.2 MII Timing FIGURE 6-2: MII Transmit Timing in MAC Mode TABLE 6-3: MII Transmit Timing in MAC Mode Values FIGURE 6-3: MII Receive Timing in MAC Mode TABLE 6-4: MII Receive Timing in MAC Mode Values FIGURE 6-4: MII Receive Timing in PHY Mode TABLE 6-5: MII Receive Timing in PHY Mode Values FIGURE 6-5: MII Transmit Timing in PHY Mode TABLE 6-6: MII Transmit Timing in PHY Mode Values 6.4.3 RMII Timing FIGURE 6-6: RMII Transmit Timing FIGURE 6-7: RMII Receive Timing TABLE 6-7: RMII Timing Values 6.4.4 MIIM Timing FIGURE 6-8: MIIM Timing TABLE 6-8: MIIM Timing Values 6.4.5 SPI Timing FIGURE 6-9: SPI Data Input Timing FIGURE 6-10: SPI Data Output Timing TABLE 6-9: SPI Timing Values 6.4.6 Auto-Negotiation Timing FIGURE 6-11: Auto-Negotiation Timing TABLE 6-10: Auto-Negotiation Timing Values 6.4.7 Trigger Output Unit and Timestamp Input Unit Timing FIGURE 6-12: Trigger Output Unit and Timestamp Input Unit Timing TABLE 6-11: Auto-Negotiation Timing Values 6.4.8 Power-up and Reset Timing FIGURE 6-13: Power-up and Reset Timing TABLE 6-12: Power-up and Reset Timing Values 6.5 Clock Specifications FIGURE 6-14: Input Reference Clock Connection Options TABLE 6-13: Reference Crystal Characteristics 7.0 Design Guidelines 7.1 Reset Circuit Guidelines FIGURE 7-1: Simple Reset Circuit FIGURE 7-2: Reset Circuit for CPU Reset Interface 7.2 Magnetics Connection and Selection Guidelines FIGURE 7-3: Typical Magnetic Interface Circuit TABLE 7-1: Magnetics Selection Criteria TABLE 7-2: Compatible Single-Port 10/100/1000 Magnetics 8.0 Package Information 8.1 Package Marking Information 8.2 Package Drawings FIGURE 8-1: Package (Drawing) FIGURE 8-2: Package (Dimensions) FIGURE 8-3: Package (Land Pattern) Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
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