Datasheet KSZ9567S (Microchip) - 10

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KSZ9567S TABLE 3-1: PIN ASSIGNMENTS Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name
1
TXRX1P_A
33
AVDDH
65
RXD6_0 (Note 3-1)
97
SDO
2
TXRX1M_A
34
TXRX4P_A
66
DVDDL
98
SDI/SDA/MDIO
3
AVDDL
35
TXRX4M_A
67
IBA (Note 3-1 )
99
VDDIO
4
TXRX1P_B
36
AVDDL
68
VDDIO
100
SCS_N
5
TXRX1M_B
37
TXRX4P_B
69
GND
101
SCL/MDC
6
TXRX1P_C
38
TXRX4M_B
70
DVDDL
102
LED5_0
7
TXRX1M_C
39
TXRX4P_C
71
VDDLS
103
LED5_1 (Note 3-1)
8
TXRX1P_D
40
TXRX4M_C
72
VDDHS
104
DVDDL
9
TXRX1M_D
41
AVDDL
73
NC
105
LED1_0
10
AVDDH
42
TXRX4P_D
74
NC
106
LED1_1 (Note 3-1)
11
DVDDL
43
TXRX4M_D
75
GND
107
GND
12
TXRX2P_A
44
AVDDH
76
S_REXT
108
NC
13
TXRX2M_A
45
DVDDL
77
GND
109
GND
14
AVDDL
46
GND
78
S_IN7M
110
DVDDL
15
TXRX2P_B
47
GND
79
S_IN7P
111
AVDDH
16
TXRX2M_B
48
TX_CLK6/REFCLKI6
80
GND
112
TXRX5P_A
17
TXRX2P_C
49
TX_EN6/TX_CTL6
81
S_OUT7P
113
TXRX5M_A
18
TXRX2M_C
50
TX_ER6
82
S_OUT7M
114
AVDDL
19
AVDDL
51
COL6
83
VDDHS
115
TXRX5P_B
20
TXRX2P_D
52
TXD6_3
84
VDDLS
116
TXRX5M_B
21
TXRX2M_D
53
TXD6_2
85
LED4_0 (Note 3-1)
117
TXRX5P_C
22
AVDDH
54
TXD6_1
86
LED4_1 (Note 3-1)
118
TXRX5M_C
23
DVDDL
55
TXD6_0
87
DVDDL
119
AVDDL
24
TXRX3P_A
56
DVDDL
88
LED3_0
120
TXRX5P_D
25
TXRX3M_A
57
RX_CLK6/REFCLKO6
89
LED3_1 (Note 3-1)
121
TXRX5M_D
26
TXRX3P_B
58
RX_DV6/CRS_DV6/
90
GPIO_1
122
AVDDH RX_CTL6
27
TXRX3M_B
59
RX_ER6
91
LED2_0 (Note 3-1)
123
GND
28
TXRX3P_C
60
CRS6
92
LED2_1 (Note 3-1)
124
AVDDL
29
TXRX3M_C
61
VDDIO
93
PME_N
125
XO
30
AVDDL
62
RXD6_3 (Note 3-1)
94
INTRP_N (Note 3-1)
126
XI
31
TXRX3P_D
63
RXD6_2 (Note 3-1)
95
SYNCLKO (Note 3-1 )
127
ISET
32
TXRX3M_D
64
RXD6_1 (Note 3-1)
96
RESET_N
128
AVDDH
Exposed Pad Must be Connected to
GND Note 3-1
This pin provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. DS00002393C-page 10  2017-2019 Microchip Technology Inc. Document Outline 1.0 Preface 1.1 Glossary of Terms TABLE 1-1: General Terms 1.2 Buffer Types TABLE 1-2: Buffer Types 1.3 Register Nomenclature TABLE 1-3: Register Nomenclature 1.4 References 2.0 Introduction 2.1 General Description FIGURE 2-1: Internal Block Diagram 3.0 Pin Descriptions and Configuration 3.1 Pin Assignments FIGURE 3-1: Pin Assignments (Top View) TABLE 3-1: Pin Assignments 3.2 Pin Descriptions TABLE 3-2: Pin Descriptions 3.2.1 Configuration Straps TABLE 3-3: Configuration Strap Descriptions 4.0 Functional Description 4.1 Physical Layer Transceiver (PHY) 4.1.1 1000BASE-T Transceiver 4.1.2 100BASE-TX Transceiver 4.1.3 10BASE-Te Transceiver 4.1.4 Auto MDI/MDI-X TABLE 4-1: MDI/MDI-X Pin Definitions 4.1.5 Pair-Swap, Alignment, and Polarity Check 4.1.6 Wave Shaping, Slew-Rate Control, and Partial Response 4.1.7 Auto-Negotiation FIGURE 4-1: Auto-Negotiation and Parallel Operation 4.1.8 Fast Link-Up 4.1.9 LinkMD® Cable Diagnostics 4.1.10 Remote PHY Loopback FIGURE 4-2: Remote PHY Loopback 4.2 LEDs 4.2.1 Single-LED Mode TABLE 4-2: Single-LED Mode Pin Definition 4.2.2 Tri-Color Dual-LED Mode TABLE 4-3: Tri-Color Dual-LED Mode Pin Definition 4.3 Media Access Controller (MAC) 4.3.1 MAC Operation 4.3.2 Inter-Packet Gap (IPG) 4.3.3 Back-Off Algorithm 4.3.4 Late Collision 4.3.5 Legal Packet Size 4.3.6 Flow Control 4.3.7 Half-Duplex Back Pressure 4.3.8 Flow Control and Back Pressure Registers TABLE 4-4: Flow Control and back Pressure Registers 4.3.9 Broadcast Storm Protection 4.3.10 Self-Address Filtering 4.4 Switch 4.4.1 Switching Engine 4.4.2 Address Lookup TABLE 4-5: Address Lookup Table Hashing Options TABLE 4-6: Reserved Multicast Address Table FIGURE 4-3: Packet Forwarding Process Flowchart TABLE 4-7: Lookup Engine Registers 4.4.3 IEEE 802.1Q VLAN TABLE 4-8: VLAN Forwarding TABLE 4-9: Hashed(DA) + FID Lookup in VLAN Mode TABLE 4-10: Hashed(SA) + FID Lookup in VLAN Mode TABLE 4-11: VLAN Registers 4.4.4 Quality-of-Service (QoS) Priority Support FIGURE 4-4: 802.p Priority Field Format 4.4.5 Traffic Conditioning & Policing 4.4.6 Spanning Tree Support TABLE 4-12: Spanning Tree States 4.4.7 Rapid Spanning Tree Support 4.4.8 Multiple Spanning Tree Support 4.4.9 Tail Tagging Mode FIGURE 4-5: Tail Tag Frame Format TABLE 4-13: Receive Tail Tag Format (from Switch to Host) TABLE 4-14: Transmit Tail Tag Format (from Host to Switch) FIGURE 4-6: PTP Mode Tail Tag Frame Format 4.4.10 IGMP Support 4.4.11 IPv6 MLD Snooping 4.4.12 Port Mirroring 4.4.13 Scheduling and Rate Limiting 4.4.14 Egress Traffic Shaping 4.4.15 Low Latency Cut-Through Mode 4.4.16 Ingress MAC Address Filtering Function 4.4.17 802.1X Access Control 4.4.18 Access Control List (ACL) Filtering TABLE 4-15: ACL Processing Entry Parameters FIGURE 4-7: ACL Structure and Example Rule Values TABLE 4-16: Matching Rule Options TABLE 4-17: ACL Matching Rule Parameters for MD = 01 TABLE 4-18: ACL Matching Rule Parameters for MD = 10 TABLE 4-19: ACL Matching Rule Parameters for MD = 11 TABLE 4-20: ACL Action Rule Parameters for Non-count Modes (MD ≠ 01 or ENB ≠ 00) TABLE 4-21: ACL Action Rule Parameters for count Mode (MD = 01 or ENB = 00) FIGURE 4-8: ACL Table Format TABLE 4-22: ACL Registers 4.5 IEEE 1588 Precision Time Protocol 4.5.1 IEEE 1588 PTP System Time Clock FIGURE 4-9: PTP System Clock Overview 4.5.2 IEEE 1588 PTP Messaging Processing 4.5.3 IEEE 1588 PTP Event Triggering and Timestamping 4.6 Audio Video Bridging and Time Sensitive Networks 4.7 NAND Tree Support TABLE 4-23: NAND Tree Test Pin Order 4.8 Clocking 4.8.1 Primary Clock 4.8.2 Port 6 RGMII/MII/RMII Clocks 4.8.3 Port 7 SGMII Clock 4.8.4 Serial Management Interface Clock 4.8.5 Synchronous Ethernet and SYNCLKO 4.9 Power FIGURE 4-10: Power Connection Diagram 4.10 Power Management TABLE 4-24: MDI/MDI-X Pin Definitions 4.10.1 Normal Operation Mode 4.10.2 Energy-Detect Mode 4.10.3 Global Soft Power-Down Mode 4.10.4 Port-Based Power Down 4.10.5 Wake on LAN (WoL) 4.11 Management Interface 4.11.1 SPI Slave Bus TABLE 4-25: Register Access using the SPI Interface FIGURE 4-11: SPI Register Read Operation FIGURE 4-12: SPI Register Write Operation 4.11.2 I2C Bus FIGURE 4-13: Single Byte Register Write FIGURE 4-14: Single Byte Register Read FIGURE 4-15: Burst Register Write FIGURE 4-16: Burst Register Read 4.11.3 MII Management (MIIM) Interface TABLE 4-26: MII Management Interface Frame Format TABLE 4-27: Standard MIIM Registers 4.12 In-Band Management FIGURE 4-17: In-Band Management Frame Format 4.13 MAC Interface (Ports 6 and 7) 4.13.1 Media Independent Interface (MII) (Port 6) TABLE 4-28: MII (PHY Mode) Connection to External MAC TABLE 4-29: MII (MAC Mode) Connection to External PHY 4.13.2 Reduced Media Independent Interface (RMII) (Port 6) TABLE 4-30: RMII Signal Descriptions TABLE 4-31: RMII Connection to External MAC TABLE 4-32: RMII Connection to External PHY 4.13.3 Reduced Gigabit Media Independent Interface (RGMII) (Port 6) TABLE 4-33: RGMII Signal Descriptions 4.13.4 Serial Gigabit Media Independent Interface (SGMII) (Port 7) 5.0 Device Registers FIGURE 5-1: Register Address Mapping FIGURE 5-2: Byte Ordering TABLE 5-1: Global Register Address Map TABLE 5-2: Port N (1-7) Register Address Map 5.1 Global Registers 5.1.1 Global Operation Control Registers (0x0000 - 0x00FF) 5.1.2 Global I/O Control Registers (0x0100 - 0x01FF) 5.1.3 Global PHY Control and Status Registers (0x0200 - 0x02FF) 5.1.4 Global Switch Control Registers (0x0300 - 0x03FF) 5.1.5 Global Switch Look Up Engine (LUE) Control Registers (0x0400 - 0x04FF) 5.1.6 Global Switch PTP Control Registers (0x0500 - 0x05FF) 5.2 Port Registers 5.2.1 Port N: Port Operation Control Registers (0xN000 - 0xN0FF) 5.2.2 Port N: Port Ethernet PHY Registers (0xN100 - 0xN1FF) 5.2.3 Port N: Port SGMII Control Registers (0xN200 - 0xN2FF) 5.2.4 Port N: Port RGMII/MII/RMII Control Registers (0xN300 - 0xN3FF) 5.2.5 Port N: Port Switch MAC Control Registers (0xN400 - 0xN4FF) TABLE 5-3: Data Rate Selection Table for Ingress and Egress Rate Limiting 5.2.6 Port N: Port Switch MIB Counters Registers (0xN500 - 0xN5FF) 5.2.7 Port N: Port Switch ACL Control Registers (0xN600 - 0xN6FF) 5.2.8 Port N: Port Switch Ingress Control Registers (0xN800 - 0xN8FF) 5.2.9 Port N: Port Switch Egress Control Registers (0xN900 - 0xN9FF) 5.2.10 Port N: Port Switch Queue Management Control Registers (0xNA00 - 0xNAFF) 5.2.11 Port N: Port Switch Address Lookup Control Registers (0xNB00 - 0xNBFF) 5.2.12 Port N: Port Switch PTP Control Registers (0xNC00 - 0xNCFF) 5.3 Tables and MIB Counters (Access) 5.3.1 Address Lookup (ALU) Table FIGURE 5-3: Address Lookup Table Configuration 5.3.2 Static Address Table 5.3.3 Reserved Multicast Address Table 5.3.4 VLAN Table FIGURE 5-4: VLAN Table Structure TABLE 5-4: VLAN Table Data Fields 5.3.5 Access Control List (ACL) Table TABLE 5-5: ACL Field Register Mapping 5.3.6 Management Information Base (MIB) Counters TABLE 5-6: MIB Counters 5.4 MDIO Manageable Device (MMD) Registers (Indirect) TABLE 5-7: MMD Register Map 5.4.1 MMD LED Mode Register 5.4.2 MMD EEE Advertisement Register 5.5 SGMII Registers (Indirect) TABLE 5-8: SGMII Register Map (Indirect) 5.5.1 SGMII Control Register 5.5.2 SGMII Status Register 5.5.3 SGMII PHY ID 1 Register 5.5.4 SGMII PHY ID 2 Register 5.5.5 SGMII Auto-Negotiation Advertisement Register 5.5.6 SGMII Auto-Negotiation Link Partner Base Ability Register 5.5.7 SGMII Auto-Negotiation Expansion Register 5.5.8 SGMII Digital Control Register 5.5.9 SGMII Auto-Negotiation Control Register 5.5.10 SGMII Auto-Negotiation Status Register 6.0 Operational Characteristics 6.1 Absolute Maximum Ratings* 6.2 Operating Conditions** 6.3 Electrical Characteristics TABLE 6-1: Electrical Characteristics 6.4 Timing Specifications 6.4.1 RGMII Timing FIGURE 6-1: RGMII Timing TABLE 6-2: RGMII Timing Values 6.4.2 MII Timing FIGURE 6-2: MII Transmit Timing in MAC Mode TABLE 6-3: MII Transmit Timing in MAC Mode Values FIGURE 6-3: MII Receive Timing in MAC Mode TABLE 6-4: MII Receive Timing in MAC Mode Values FIGURE 6-4: MII Receive Timing in PHY Mode TABLE 6-5: MII Receive Timing in PHY Mode Values FIGURE 6-5: MII Transmit Timing in PHY Mode TABLE 6-6: MII Transmit Timing in PHY Mode Values 6.4.3 RMII Timing FIGURE 6-6: RMII Transmit Timing FIGURE 6-7: RMII Receive Timing TABLE 6-7: RMII Timing Values 6.4.4 MIIM Timing FIGURE 6-8: MIIM Timing TABLE 6-8: MIIM Timing Values 6.4.5 SPI Timing FIGURE 6-9: SPI Data Input Timing FIGURE 6-10: SPI Data Output Timing TABLE 6-9: SPI Timing Values 6.4.6 Auto-Negotiation Timing FIGURE 6-11: Auto-Negotiation Timing TABLE 6-10: Auto-Negotiation Timing Values 6.4.7 Trigger Output Unit and Timestamp Input Unit Timing FIGURE 6-12: Trigger Output Unit and Timestamp Input Unit Timing TABLE 6-11: Auto-Negotiation Timing Values 6.4.8 Power-up and Reset Timing FIGURE 6-13: Power-up and Reset Timing TABLE 6-12: Power-up and Reset Timing Values 6.5 Clock Specifications FIGURE 6-14: Input Reference Clock Connection Options TABLE 6-13: Reference Crystal Characteristics 7.0 Design Guidelines 7.1 Reset Circuit Guidelines FIGURE 7-1: Simple Reset Circuit FIGURE 7-2: Reset Circuit for CPU Reset Interface 7.2 Magnetics Connection and Selection Guidelines FIGURE 7-3: Typical Magnetic Interface Circuit TABLE 7-1: Magnetics Selection Criteria TABLE 7-2: Compatible Single-Port 10/100/1000 Magnetics 8.0 Package Information 8.1 Package Marking Information 8.2 Package Drawings FIGURE 8-1: Package (Drawing) FIGURE 8-2: Package (Dimensions) FIGURE 8-3: Package (Land Pattern) Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service