Datasheet KSZ9893RNX (Microchip) - 3

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KSZ9893RNX 1.0 INTRODUCTION 1.1 General Description
The KSZ9893RNX is a highly-integrated, IEEE 802.3 compliant networking device that incorporates a layer-2+ man- aged Gigabit Ethernet switch, two 10BASE-T/100BASE-TX/1000BASE-T physical layer transceivers (PHYs) and asso- ciated MAC units, and one MAC port with a configurable RGMII/MII/RMII interface for direct connection to a host processor/controller, another Ethernet switch, or an Ethernet PHY transceiver. The KSZ9893RNX is built upon industry-leading Ethernet technology, with features designed to offload host processing and streamline the overall design: • Non-blocking wire-speed Ethernet switch fabric • Full-featured forwarding and filtering control, including port-based Access Control List (ACL) filtering • Full VLAN and QoS support • Traffic prioritization with per-port ingress/egress queues and by traffic classification • Spanning Tree support for RSTP and MSTP • IEEE 802.1X port-based authentication support A host processor can access all KSZ9893RNX registers for control over all PHY, MAC, and switch functions. Full register access is available via the integrated SPI or I2C interfaces, and by in-band management via any one of the data ports. PHY register access is provided by a MIIM interface. Flexible digital I/O voltage allows the MAC port to interface directly with a 1.8/2.5/3.3V host processor/controller/FPGA. Additionally, a robust assortment of power-management features including IEEE 802.3az Energy-Efficient Ethernet (EEE) for power savings with idle link, and Wake-on-LAN (WoL) for low power standby operation, have been designed to satisfy energy-efficient system requirements. The KSZ9893RNX is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal block diagram of the KSZ9893RNX is shown in Figure 1-1.
FIGURE 1-1: INTERNAL BLOCK DIAGRAM GMAC 3
RGMII/MII/RMII Port 1
10/100/1000 PHY 1 GMAC 1
. Address
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S, Etc Lookup
gin
, Qoent
 En
MIB em Counters Port 2
10/100/1000 GMAC 2 tch PHY 2
anag
Swi
 Me Frame u Buffers Que Control Queue Registers Mgmt.
KSZ9893RNX
SPI/I2C/MIIM  2016 Microchip Technology Inc. DS00002318A-page 3 Document Outline Highlights Target Applications Features 1.0 Introduction 1.1 General Description FIGURE 1-1: Internal Block Diagram 2.0 Package Information 2.1 Package Drawings FIGURE 2-1: Package (Drawing) FIGURE 2-2: Package (Dimensions) FIGURE 2-3: Package (Land Pattern) Appendix A: PRODUCT BRIEF Revision History The Microchip Web Site Product Identification System Worldwide Sales and Service