I 1) MI Block Diagram o urb -08-1 I/T I/RMI n 1.5 (07 MI ingle S MII/Turbo MII to PHY or Revisio MII/RMII/Turbo MII to MAC itch with w S net Virtual PHY her MDIO Registers 4 Queu Ethernet D 4 Queu D MDIO 10/100 Por Por MDIO Qo yna Qo yna MII ged Et To optional SMI Master PHY MII 10/100 10/100 t 1 S m S m t 0 Data MII MAC es i es i MAC Registers c c Path Mode MDIO MUX PHY Management Mode Configuration Interface (PMI) Search Straps /100 Mana Switch Engine Engine 10 rt Mode Configuration SMI (slave) o MDIO Buffer Manager Frame Straps P Buffers Controller e 4 Que Dynam Por QoS Switch Register 4 PREVIEW or Thre MII t 10/100 I2C Slave 2 Registers Access u act Ethernet 10/100 MAC es ic Controller (CSRs) MUX PHY MDIO System Registers Switch Fabric Registers PRODUCT all Form F (CSRs) m S EEPROM Loader To optional EEPROM System GP Timer (via I2C master) System GPIO/LED Clocks/ EEPROM Controller I2C Interrupt Control er Reset/PME I2C (master) To optional CPU LAN9303/ Controller Free-Run Controller serial management Clk LAN9303i (via I2C slave) To optional GPIOs/LEDs IRQ External LAN9303i 25MHz Crystal Figure 1 Internal Block Diagram SMSC LAN9303/ Document Outline General Description Block Diagram Figure 1 Internal Block Diagram Package Outline 56-QFN Package Outline Figure 2 56-QFN Package Definition Table 1 56-QFN Dimensions Figure 3 56-QFN Recommended PCB Land Pattern
