Datasheet VSC7440 (Microchip) - 29

Functional Descriptions the frame’s COS and color indications such as DEI, PCP, and DSCP. Departure statistics are also kept based on the classified VLAN. •
Basic VLAN Tagging Operations (Port-based)
By default, the egress VLAN actions are determined by the egress port settings and classified VLAN. These include basic VLAN operations such as pushing a VLAN tag, untagging for specific VLANs, and simple translations of DEI, PCP, and DSCP. •
Advanced VLAN Tagging Operations (Port-based and VCAP-based)
By using the egress VCAP ES0, significantly more advanced VLAN tagging operations can be achieved. ES0 enables pushing up to three VLAN tags and flexible VLAN tag translation for VLAN tag/TPID, PCP, DEI, and DSCP control. The lookup by VCAP ES0 includes classified VLAN, egress port, and COS/color indications. •
Layer 3 Forwarding (Routing) Operations
Supports per-router-leg control of Ethernet link layer encapsulation and VID, as well as modification of other Layer 3 fields such as IPv4 TTL, IPv4 checksum, and IPv6 hop limit. •
PTP (IEEE 1588) Operations
PTP PDU modifications include insertion/update of time stamps and correction fields, as well as updating the UDP checksum. The rewriter pads frames to minimum legal size if needed, and updates the FCS if the frame was modified before the frame is transmitted. The egress port module controls the flow control exchange of pause frames with a neighboring device when the interconnection link operates in full-duplex flow control mode.
3.2.9 CPU Port Module
The CPU port module (DEVCPU) contains eight CPU extraction queues and two CPU injection queues. These queues provide an interface for exchanging frames between the internal CPU system and the switch core. An external CPU using the serial interface can also inject and extract frames to and from the switch core by using the CPU port module. In addition, any Ethernet interface on the device can be used for extracting and injecting frames. The Ethernet interface used in this way is called the Node Processor Interface (NPI) and is typically connected to an external CPU. Injected frames may be prepended with an injection header to control processing and forwarding of these frames. Extracted frames may be prepended with an extraction header to supply frame arrival and classification information associated with each frame. These headers may be used by internal CPU or external CPU. The switch core can intercept a variety of different frame types and copy or redirect these to the CPU extraction queues. The classifier can identify a set of well-known frames, such as IEEE reserved destination MAC addresses (BPDUs, GARPs, CCM/Link trace), as well as IP-specific frames (IGMP, MLD). Security VCAP IS2 provides another flexible way of intercepting all kinds of frames, such as specific OAM frames, ARP frames or explicit applications based on TCP/UDP port numbers. In addition, frames can be intercepted based on the MAC table, the VLAN table, or the learning process. Whenever a frame is copied or redirected to the CPU, a CPU extraction queue number is associated with the frame and used by the CPU port module when enqueuing the frame into the eight CPU extraction queues. The CPU extraction queue number is programmable for every interception option in the switch core.
3.2.10 Synchronous Ethernet and Precision Time Protocol (PTP)
The device supports Synchronous Ethernet and IEEE 1588 Precision Time Protocol (PTP) for synchronizing network timing throughout a network. Synchronous Ethernet allows for the transfer of precise network timing (frequency) using physical Ethernet link timing. Each switch port can recover its ingress clock and output the recovered clock to one of up to four recovered clock output pins. External circuitry can then generate a stable reference clock input used for egress and core logic timing. The Precision Time Protocol (PTP) allows for the transfer of precise network timing (frequency) and time of day (phase) using Ethernet packets. PTP can operate as a one-step clock or a two-step clock. For VMDS-10492 VSC7440 Datasheet Revision 4.2 12 Document Outline 1 Revision History 1.1 Revision 4.2 1.2 Revision 4.1 1.3 Revision 4.0 2 Product Overview 2.1 General Features 2.1.1 Layer 2 and Layer 3 Forwarding 2.1.2 Timing and Synchronization 2.1.3 Quality of Service 2.1.4 Security 2.1.5 Management 2.1.6 Product Parameters 2.2 Applications 3 Functional Descriptions 3.1 Register Notations 3.2 Functional Overview 3.2.1 Frame Arrival in Ports and Port Modules 3.2.2 Basic Classification 3.2.3 Security and Control Protocol Classification 3.2.4 Policing 3.2.5 Layer 2 Forwarding 3.2.6 Layer 3 Forwarding 3.2.7 Shared Queue System and Hierarchical Scheduler 3.2.8 Rewriter and Frame Departure 3.2.9 CPU Port Module 3.2.10 Synchronous Ethernet and Precision Time Protocol (PTP) 3.2.11 CPU Subsystem 3.3 Frame Headers 3.3.1 Internal Frame Header Placement 3.3.2 Internal Frame Header Layout 3.3.3 VStaX Header 3.4 Port Numbering and Mappings 3.4.1 Supported SerDes Interfaces 3.4.2 Dual-Media Mode 3.4.3 10G Modes 3.4.4 Logical Port Numbers 3.5 SERDES1G 3.6 SERDES6G 3.7 SERDES10G 3.8 Copper Transceivers 3.8.1 Register Access 3.8.2 Cat5 Twisted Pair Media Interface 3.8.3 Wake-On-LAN and SecureOn 3.8.4 Ethernet Inline Powered Devices 3.8.5 IEEE 802.3af PoE Support 3.8.6 ActiPHY™ Power Management 3.8.7 Testing Features 3.8.8 VeriPHY™ Cable Diagnostics 3.9 DEV1G and DEV2G5 Port Modules 3.9.1 MAC 3.9.2 Half-Duplex Mode 3.9.3 Physical Coding Sublayer (PCS) 3.9.4 Port Statistics 3.10 DEV10G Port Module 3.10.1 MAC 3.10.2 Physical Coding Sublayer (PCS) 3.10.3 Port Statistics 3.11 Assembler 3.11.1 Setting Up a Port in the Assembler 3.11.2 Setting Up a Port for Frame Injection 3.11.3 Setting Up MAC Control Sublayer PAUSE Frame Detection 3.11.4 Setting Up PFC 3.11.5 Setting Up Assembler Port Statistics 3.11.6 Setting Up the Loopback Path 3.12 Versatile Content-Aware Processor (VCAP) 3.12.1 Configuring VCAP 3.12.2 Wide VCAP Entries and Actions 3.12.3 Individual VCAPs 3.12.4 VCAP Programming Examples 3.13 Pipeline Points 3.13.1 Pipeline Definitions 3.14 Analyzer 3.14.1 Initializing the Analyzer 3.15 VCAP CLM Keys and Actions 3.15.1 Keys Overview 3.15.2 VCAP CLM X1 Key Details 3.15.3 VCAP CLM X2 Key Details 3.15.4 VCAP CLM X4 Key Details 3.15.5 VCAP CLM X8 Key Details 3.15.6 VCAP CLM X16 Key Details 3.15.7 VCAP CLM Actions 3.16 Analyzer Classifier 3.16.1 Basic Classifier 3.16.2 VCAP CLM Processing 3.16.3 QoS Mapping Table 3.16.4 Analyzer Classifier Diagnostics 3.17 VLAN and MSTP 3.17.1 Private VLAN 3.17.2 VLAN Pseudo Code 3.18 VCAP LPM: Keys and Action 3.18.1 VCAP LPM SGL_IP4 Key Details 3.18.2 VCAP LPM DBL_IP4 Key Details 3.18.3 VCAP LPM SGL_IP6 Key Details 3.18.4 VCAP LPM DBL_IP6 Key Details 3.18.5 VCAP LPM Actions 3.19 IP Processing 3.19.1 IP Source/Destination Guard 3.19.2 IP Routing 3.19.3 Statistics 3.19.4 IGMP/MLD Snooping Switch 3.20 VCAP IS2 Keys and Actions 3.20.1 VCAP IS2 Keys 3.20.2 VCAP IS2 Actions 3.21 Analyzer Access Control Lists 3.21.1 VCAP IS2 3.21.2 Analyzer Access Control List Frame Rewriting 3.22 Analyzer Layer 2 Forwarding and Learning 3.22.1 Analyzer MAC Table 3.22.2 MAC Table Updates 3.22.3 CPU Access to MAC Table 3.22.4 SCAN Command 3.22.5 Forwarding Lookups 3.22.6 Source Check and Automated Learning 3.22.7 Automated Aging (AUTOAGE) 3.22.8 Interrupt Handling 3.23 Analyzer Access Control Forwarding, Policing, and Statistics 3.23.1 Mask Handling 3.23.2 Policing 3.23.3 Analyzer Statistics 3.23.4 Analyzer sFlow Sampling 3.23.5 Mirroring 3.24 Shared Queue System and Hierarchical Scheduler 3.24.1 Analyzer Result 3.24.2 Buffer Control 3.24.3 Forwarding 3.24.4 Congestion Control 3.24.5 Queue Mapping 3.24.6 Queue Congestion Control 3.24.7 Scheduling 3.24.8 Queue System Initialization 3.24.9 Miscellaneous Features 3.25 Automatic Frame Injector 3.25.1 Injection Tables 3.25.2 Frame Table 3.25.3 Delay Triggered Injection 3.25.4 Timer Triggered Injection 3.25.5 Injection Queues 3.25.6 Adding Injection Frame 3.25.7 Starting Injection 3.25.8 Stopping Injection 3.25.9 Removing Injection Frames 3.25.10 Port Parameters 3.26 Rewriter 3.26.1 Rewriter Operation 3.26.2 Supported Ports 3.26.3 Supported Frame Formats 3.26.4 Rewriter Initialization 3.26.5 VCAP_ES0 Lookup 3.26.6 Mapping Tables 3.26.7 VLAN Editing 3.26.8 DSCP Remarking 3.26.9 VStaX Header Insertion 3.26.10 Forwarding to GCPU 3.26.11 Layer 3 Routing 3.26.12 Mirror Frames 3.26.13 Internal Frame Header Insertion 3.26.14 Frame Injection from Internal CPU 3.27 Disassembler 3.27.1 Setting Up Ports 3.27.2 Maintaining the Cell Buffer 3.27.3 Setting Up MAC Control Sublayer PAUSE Function 3.27.4 Setting up Flow Control in Half-Duplex Mode 3.27.5 Setting Up Frame Aging 3.27.6 Setting Up Transmit Data Rate Limiting 3.27.7 Error Detection 3.28 Layer 1 Timing 3.29 Hardware Time Stamping 3.29.1 One-Step Functions 3.29.2 Calculation Overview 3.29.3 Detecting Calculation Issues 3.29.4 Two-Step Functions 3.29.5 Time of Day Time Stamping 3.29.6 Time of Day Generation 3.29.7 Multiple PTP Time Domains 3.29.8 Register Interface to 1588 Functions 3.29.9 Configuring I/O Delays 3.30 VRAP Engine 3.30.1 VRAP Request Frame Format 3.30.2 VRAP Response Frame Format 3.30.3 VRAP Header Format 3.30.4 VRAP READ Command 3.30.5 VRAP READ-MODIFY-WRITE Command 3.30.6 VRAP IDLE Command 3.30.7 VRAP PAUSE Command 3.31 Energy Efficient Ethernet 3.32 CPU Injection and Extraction 3.32.1 Frame Injection 3.32.2 Frame Extraction 3.32.3 Forwarding to CPU 3.32.4 Automatic Frame Injection (AFI) 3.33 Priority-Based Flow Control (PFC) 3.33.1 PFC Pause Frame Generation 3.33.2 PFC Frame Reception 3.34 Protection Switching 3.34.1 Ethernet Ring Protection Switching 3.34.2 Link Aggregation 3.34.3 Port Protection Switching 3.35 Low Power Mode 3.35.1 One-Time Configurations for Low Power Mode 3.35.2 General Considerations in Low Power Mode 3.36 Clocking and Reset 3.36.1 Pin Strapping 4 VCore-III System and CPU Interfaces 4.1 VCore-III Configurations 4.2 Clocking and Reset 4.2.1 Watchdog Timer 4.3 Shared Bus 4.3.1 VCore-III Shared Bus Arbitration 4.3.2 Chip Register Region 4.3.3 SI Flash Region 4.3.4 DDR3/DDR3L Region 4.3.5 PCIe Region 4.4 VCore-III CPU 4.4.1 Little Endian and Big Endian Support 4.4.2 Software Debug and Development 4.5 External CPU Support 4.5.1 Register Access and Multimaster Systems 4.5.2 Serial Interface in Slave Mode 4.5.3 MIIM Interface in Slave Mode 4.5.4 Access to the VCore Shared Bus 4.5.5 Mailbox and Semaphores 4.6 PCIe Endpoint Controller 4.6.1 Accessing Endpoint Registers 4.6.2 Enabling the Endpoint 4.6.3 Base Address Registers Inbound Requests 4.6.4 Outbound Interrupts 4.6.5 Outbound Access 4.6.6 Power Management 4.6.7 Device Reset Using PCIe 4.7 Frame DMA 4.7.1 DMA Control Block Structures 4.7.2 Enabling and Disabling FDMA Channels 4.7.3 Channel Counters 4.7.4 FDMA Events and Interrupts 4.7.5 FDMA Extraction 4.7.6 FDMA Injection 4.7.7 Manual Mode 4.8 VCore-III System Peripherals 4.8.1 SI Boot Controller 4.8.2 SI Master Controller 4.8.3 DDR3/DDR3L Memory Controller 4.8.4 Timers 4.8.5 UARTs 4.8.6 Two-Wire Serial Interface 4.8.7 MII Management Controller 4.8.8 GPIO Controller 4.8.9 Serial GPIO Controller 4.8.10 Fan Controller 4.8.11 Temperature Sensor 4.8.12 Memory Integrity Monitor 4.8.13 Interrupt Controller 5 Registers 6 Electrical Specifications 6.1 DC Characteristics 6.1.1 Reference Clock 6.1.2 PLL Clock Output 6.1.3 DDR3/DDR3L SDRAM Interface 6.1.4 SERDES1G 6.1.5 SERDES6G 6.1.6 SERDES10G 6.1.7 GPIO, SI, JTAG, and Miscellaneous Signals 6.1.8 Thermal Diode 6.2 AC Characteristics 6.2.1 Reference Clock 6.2.2 PLL Clock Outputs 6.2.3 SERDES1G 6.2.4 SERDES6G 6.2.5 SERDES10G 6.2.6 Reset Timing 6.2.7 MII Management 6.2.8 Serial Interface (SI) Boot Master Mode 6.2.9 Serial Interface (SI) Master Mode 6.2.10 Serial Interface (SI) for Slave Mode 6.2.11 DDR SDRAM Interface 6.2.12 JTAG Interface 6.2.13 Serial Inputs/Outputs 6.2.14 Recovered Clock Outputs 6.2.15 Two-Wire Serial Interface 6.2.16 IEEE 1588 Time Tick Outputs 6.3 Current and Power Consumption 6.3.1 Current Consumption 6.3.2 Power Consumption 6.3.3 Power Supply Sequencing 6.4 Operating Conditions 6.5 Stress Ratings 7 Pin Descriptions 7.1 Pin Diagram 7.2 Pins by Function 7.2.1 DDR SDRAM Interface 7.2.2 General-Purpose Inputs and Outputs 7.2.3 JTAG Interface 7.2.4 MII Management Interface 7.2.5 Miscellaneous 7.2.6 PCI Express Interface 7.2.7 Power Supplies and Ground 7.2.8 SERDES1G 7.2.9 SERDES6G 7.2.10 SERDES10G 7.2.11 Serial CPU Interface 7.2.12 System Clock Interface 7.2.13 Twisted Pair Interface 7.3 Pins by Number 7.4 Pins by Name 8 Package Information 8.1 Package Drawing 8.2 Thermal Specifications 8.3 Moisture Sensitivity 9 Design Guidelines 9.1 Power Supplies 9.2 Power Supply Decoupling 9.2.1 Reference Clock 9.2.2 Single-Ended REFCLK Input 9.3 Interfaces 9.3.1 General Recommendations 9.3.2 SerDes Interfaces (SGMII, 2.5G, 10G) 9.3.3 Serial Interface 9.3.4 PCI Express Interface 9.3.5 Two-Wire Serial Interface 9.3.6 DDR3 SDRAM Interface 9.3.7 Thermal Diode External Connection 10 Design Considerations 11 Ordering Information