link to page 7 LT8331 OPERATION The LT8331 uses a fixed frequency, current mode con- the LT8331 is in an inverting configuration, the FBX pin trol scheme to provide excellent line and load regula- is pulled down to –0.80V by a voltage divider from VOUT tion. Operation can be best understood by referring to to GND. Amplifier A1 becomes inactive and amplifier A2 the Block Diagram. An oscillator (with frequency pro- performs (non-inverting) amplification from FBX to VC. grammed by a resistor at the RT pin) turns on the inter- If the EN/UVLO pin voltage is below 1.6V, the LT8331 nal power switch at the beginning of each clock cycle. enters undervoltage lockout (UVLO), and stops switch- Current in the inductor then increases until the current ing. When the EN/UVLO pin voltage is above 1.74V (typi- comparator trips and turns off the power switch. The cal), the LT8331 resumes switching. If the EN/UVLO pin peak inductor current at which the switch turns off is voltage is below 0.2V, the LT8331 draws less than 1µA controlled by the voltage on the internal VC node. The from V error amplifier servos the VC node by comparing the IN. voltage on the FBX pin with an internal reference voltage For the SYNC/MODE pin tied to ground, the LT8331 pro- (1.60V or –0.80V, depending on the chosen topology). vides low output ripple Burst Mode operation with ultra When the load current increases it causes a reduction low quiescent current at light loads. For the SYNC/MODE in the FBX pin voltage relative to the internal reference. pin tied to INTVCC, the LT8331 uses pulse-skipping mode, This causes the error amplifier to increase the VC voltage at the expense of hundreds of microamps, to maintain until the new load current is satisfied. In this manner, output voltage regulation at light loads by skipping switch the error amplifier sets the correct peak switch current pulses. For the SYNC/MODE pin driven by an external level to keep the output in regulation. clock, the converter switching frequency is synchronized to that clock and pulse-skipping mode is also enabled. The LT8331 is capable of generating either a positive or negative output voltage with a single FBX pin. It can be The LT8331 includes a BIAS pin to improve efficiency configured as a boost, SEPIC or flyback converter to gen- across all loads. The INTVCC supply current can be erate a positive output voltage, or as an inverting converter drawn from the BIAS pin instead of the VIN pin for 4.4V to generate a negative output voltage. When configured ≤ BIAS ≤ VIN. as a SEPIC converter, as shown in the Block Diagram, the Protection features ensure the immediate disable of FBX pin is pulled up to the internal bias voltage of 1.60V switching and reset of the SS pin for any of the following by a voltage divider (R1 and R2) connected from VOUT faults: internal reference UVLO, INTV to GND. Amplifier A2 becomes inactive and amplifier A1 CC UVLO, switch cur- rent > 1.9× maximum limit, EN/UVLO < 1.6V or junction performs (inverting) amplification from FBX to VC. When temperature > 170°C. Rev. C 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
