Datasheet ADUCM355 (Analog Devices) - 11

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Data Sheet ADuCM355 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DAC AC Characteristics Output Settling Time 1.5 sec Settled to ±2 LSB (12-bit) for ¼ of full scale to ¾ of full scale, with 1 kΩ load on amplifier output, 0.1 μF capacitors connected to VBIASx and VZEROx pins, LPTIASWx, Bits[13:12] = 11 500 μS Settled to ±2 LSB (12-bit) for ¼ of full scale to ¾ of full scale, with 1 kΩ load on amplifier output, capacitors on VBIASx and VZEROx disconnected, LPTIASWx, Bits[13:12] = 00 Glitch Energy ±5 nV/sec 1 LSB change when the maximum number of bits changes simultaneously in the LPDACDATx register, switch to external capacitors on VBIASx and VZEROx opened, no capacitors on CEx/RCx_1 pins EXCITATION DAC, PGA, AND Use HSDACDAT range of 0x200 to 0xE00, RECONSTRUCTION FILTER (RCF) specified for gain = 2, (HSDACCON, Bit 12 and SPECIFICATIONS HSDACCON, Bit 0 = 0) and gain = 0.05, (HSDACCON, Bit 12 and HSDACCON, Bit 0 = 1) DAC Common-Mode Voltage Range1 0.2 AVDD − V Set by excitation amplifiers N node (refer 0.6 to the ADuCM355 Hardware Reference Manual) Resolution1 12 Bits Differential Nonlinearity9 DNL +1/−0.99 LSB Guaranteed monotonic, gain = 2 ±7 ±14 LSB Gain = 0.05 Relative Accuracy1, 9 INL ±2 ±3 LSB Gain = 2 ±8 ±18 LSB Gain = 0.05 Full Scale12 Positive 607 mV Gain = 2, DAC code = 0xE00 15.1 mV Gain = 0.05, DAC code = 0xE00 Negative −607 mV Gain = 2, DAC code = 0x200 −15. mV Gain = 0.05, DAC code = 0x200 1 Gain Error Drift1 Gain = 2 11.5 μV/°C Gain = 0.05 0.33 μV/°C Offset Error (Midscale) Measured at an output of the excitation loop across RCALx, DAC code = 0x800, not calibrated in production, offset calibration can remove this error ±25 mV Gain = 2 ±1 mV Gain = 0.05 Offset Error Drift1 Gain = 2 40 μV/°C Gain = 0.05 5 μV/°C DC Power Supply Rejection Ratio DC PSRR 70 dB DC variation due to AVDD supply changes PGA Programmable Gain 0.05 2 RCF 3 dB Corner Frequency Accuracy ±5 % Programmable to 50 kHz, 100 kHz, and 250 KHz Allowed External Load Capacitance1 SEx, DEx, AINx, and RCALx pins <80 kHz (Low Power Mode) 100 pF >80 kHz (High Power Mode) 80 pF Rev. C | Page 11 of 28 Document Outline FEATURES APPLICATIONS SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS RMS NOISE RESOLUTION OF ADC TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION RECOMMENDED CIRCUIT AND COMPONENT VALUES OUTLINE DIMENSIONS ORDERING GUIDE