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Datasheet LTM4657 (Analog Devices) - 7

ПроизводительAnalog Devices
Описание20VIN, 8A Step-Down DC/DC µModule Regulator
Страниц / Страница28 / 7 — PIN FUNCTIONS VIN (D3-D4, E3-E4, F4, G4):. GND (B2, B6, C3-C7, D5-D7, …
Формат / Размер файлаPDF / 2.0 Мб
Язык документаанглийский

PIN FUNCTIONS VIN (D3-D4, E3-E4, F4, G4):. GND (B2, B6, C3-C7, D5-D7, E5-E7, F5-F7, G6-G7):. PGOOD (B5):. – (A7):. INTV. SENSE

PIN FUNCTIONS VIN (D3-D4, E3-E4, F4, G4): GND (B2, B6, C3-C7, D5-D7, E5-E7, F5-F7, G6-G7): PGOOD (B5): – (A7): INTV SENSE

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Текстовая версия документа

link to page 10 link to page 10 LTM4657
PIN FUNCTIONS VIN (D3-D4, E3-E4, F4, G4):
Power input pins connect to
GND (B2, B6, C3-C7, D5-D7, E5-E7, F5-F7, G6-G7):
the drain of the internal top MOSFET and signal VIN to the Power Ground Pins for Both Input and Output Returns. internal 3.3V regulator for the control circuitry for each Use large PCB copper areas to connect all GND together. switching mode regulator channel. Apply input voltages
PGOOD (B5):
Output Power Good Pin with Open-Drain between these pins and GND pins. Recommend placing Logic. PGOOD is pulled to ground when the voltage on input decoupling capacitance directly between VIN pins the FB pin is not within ±8% of the internal 0.5V reference. and GND pins.
T – (A7):
Low Side of the Internal Temperature
INTV SENSE CC (B3):
Internal 3.3V Regulator Output of the Monitor. Switching Mode Regulator Channel. The internal power drivers and control circuits are powered from this voltage.
SW (B7):
Switching node of each channel that is used Decouple each pin to GND with a minimum of 2.2µF local for testing purposes. Also an R-C snubber network can low ESR ceramic capacitor. be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information
RUN (B4):
Run Control Input Pin. Enable regulator opera- section. tion by tying the specific RUN pin above 1.2V. Tying it below 1.1V shuts down the specific regulator channel.
T + SENSE (A6):
Temperature Monitor Pin. An internal diode connected PNP transistor is placed between T + SENSE and T – SENSE pins. See the Applications Information section. Rev 0 For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Package Photo Design Resources Related Parts
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