link to page 22 link to page 22 link to page 22 link to page 20 link to page 20 HIP2210, HIP2211 1. Overview HIP2211FR8Z HIP2210FRTZ (8 Ld 4x4 DFN) (10 Ld 4x4 TDFN) Top View Top View VDD 1 8 LOVDD110LOHB29HBVSS 2 7 VSS EPAD HO38EPADPWMHO 3 6 LIHS47ENHS 4 5 HIVREF56RDT1.4Pin DescriptionsPin NumberHIP2210HIP2211PinName 10 Ld DFN 10 Ld DFN 8 Ld SOIC 8 Ld DFNDescription VDD 1 1 1 1 Analog input supply voltage and positive supply for the lower gate driver. Decouple this pin to ground with a 4.7µF or larger high-frequency ceramic capacitor to VSS. An additional 0.1µF ceramic decoupling capacitor placed close to VDD and VSS pin is recommended. HB 2 2 2 2 High-side bootstrap supply voltage for the upper gate driver referenced to HS. Connect the bootstrap capacitor to this pin and HS. HO 3 3 3 3 High-side output driver. Connect to the gate of the high-side NMOS FET. HS 4 4 4 4 High-side gate driver reference node. Connect to the source of the high-side NMOS FET. Connect the bootstrap capacitor to this pin and HB. HI - 7 5 5 High-side driver logic input. 3.3V logic compatible and VDD tolerant. LI - 8 6 6 Low-side driver logic input. 3.3V logic compatible and VDD tolerant. VREF 5 - - - Reference voltage that sets the PWM logic level thresholds. Analog supply range of 2.7V to 5.5V. Decouple VREF to VSS with a 0.1µF ceramic capacitor. If VREF is below 2.7V, the PWM inputs are ignored and HO = LO = 0. An internal 100kΩ pull-down resistor places VREF in the low state when the pin is left floating. RDT 6 - - - Programmable dead time control pin. Place a resistor from the RDT pin to VSS to set the
dead time from 35ns to 350ns. The resistor range is 10kΩ to 100kΩ. Short the RDT pin to VSS to set the dead time to 15ns. See “PCB Layout Guidelines” on page 22 and “RDT and Dead Time Delay (HIP2210 Only)” on page 20 for more information. EN 7 - - - Output enable pin. When EN is low, HO = LO = 0. An internal 100kΩ pull-down resistor places EN in the low state when the pin is left floating. Output is enabled when EN is high (VDD tolerant). PWM 8 - - - Tri-level PWM input. Logic high drives HO high and LO low. Logic low drives HO low and LO high. In the mid-level state, both outputs are driven low. An internal resistor network biases the PWM pin to 50% of VREF when the pin is left floating to set the mid-level state. VSS 9 9 7 7 Ground reference for the VDD supply. When EPAD is available, connect VSS to EPAD. LO 10 10 8 8 Low-side output driver. Connect to the gate of the low-side NMOS FET. NC - 5, 6 - - No Connect. No electrical connection from this pin to the IC. - EPAD EPAD - EPAD The EPAD is electrically isolated. Connect the EPAD to the PCB ground plane with thermal vias for heat removal. See “PCB Layout Guidelines” on page 22 for more information. FN9347 Rev.1.01 Page 5 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings
