Datasheet NV6125 (Navitas Semiconductor) - 10

NV6125 NV6125 7. Internal Schematic, Pin Configurations and Functions
Package Top View
Pin I/O(1) Description Number Symbol
Metal cooling pad on bottom of package for thermal management.
CP must
1,7,8,9,12,13,14,24,25,26,29,30,31 CP T
be connected to Source or circuit PGND. Do not leave CP unconnected or floating!
2,3,4,5,6 S O, G Source of power FET & GaN IC supply ground. 10 D I Gate drive supply voltage set pin (connect 6.2 V Zener to GND). Z 11 V I Gate drive supply voltage. Gate drive turn-on current set pin (using R ). DD DD 27 PWM I PWM input 28 V P Supply voltage (10V to 24V) CC 15,16,17,18,19,20,21,22,23 D P Drain of power FET (1) I = Input, O = Output, P = Power, G = GaN IC Ground, T = Thermal
Final Datasheet 10 Rev Nov 21, 2019