ADL5511Data SheetParameter TestConditions/CommentsMinTypMaxUnit ENABLE INTERFACE Pin ENBL Logic Level to Enable Power 4.75 V ≤ VPOS ≤ 5.25 V 3.6 V Logic Level to Disable Power 4.75 V ≤ VPOS ≤ 5.25 V 2.0 V POWER SUPPLIES Operating Range −40°C < TA < +85°C 4.75 5.25 V Quiescent Current RFIN < −10 dBm, ENBL high 21.5 mA RFIN < −10 dBm, ENBL low 26 μA RFIN = 15 dBm, ENBL high 43.8 mA Rev. D | Page 6 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Circuit Description Envelope Propagation Delay RMS Circuit Description RMS Filtering Output Drive Capability and Buffering Viewing the Envelope on an Oscilloscope Applications Information Basic Connections Operation Below 1 GHz/Envelope Filtering Choosing a Value for the RMS Averaging Capacitor (CFLT4) Envelope Tracking Accuracy Time Domain Envelope Tracking Accuracy VRMS and VENV Output Offset Device Calibration and Error Calculation Error vs. Frequency Evaluation Board Outline Dimensions Ordering Guide
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