Datasheet AD8363 (Analog Devices) - 14

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AD8363 Data Sheet THEORY OF OPERATION
The computational core of the AD8363 is a high performance The output of the VGA, VSIG, is applied to a wideband square AGC loop. As shown in Figure 33, the AGC loop comprises a law detector. The detector provides the true rms response of the wide bandwidth variable gain amplifier (VGA), square law RF input signal, independent of waveform. The detector output, detectors, an amplitude target circuit, and an output driver. For ISQR, is a fluctuating current with positive mean value. The a more detailed description of the functional blocks, see the difference between ISQR and an internally generated current, AD8362 data sheet. ITGT, is integrated by CF and the external capacitor attached to The nomenclature used in this data sheet to distinguish the CLPF pin at the summing node. CF is an on-chip 25 pF filter between a pin name and the signal on that pin is as follows: capacitor, and CLPF, the external capacitance connected to the CLPF pin, can be used to arbitrarily increase the averaging time The pin name is all uppercase (for example, VPOS, while trading off with the response time. When the AGC loop is COMM, and VOUT). at equilibrium The signal name or a value associated with that pin is the pin mnemonic with a partial subscript (for example, C Mean(ISQR) = ITGT (3) LPF, CHPF, and VOUT). This equilibrium occurs only when
SQUARE LAW DETECTOR AND AMPLITUDE TARGET
Mean(V 2 2 SIG ) = VTGT (4) The VGA gain has the form where VTGT is the voltage presented at the VTGT pin. This pin G can conveniently be connected to the VREF pin through a voltage SET = GO exp(−VSET/VGNS) (1) divider to establish a target rms voltage VATG of ~70 mV rms, when where: VTGT = 1.4 V. GO is the basic fixed gain. V Because the square law detectors are electrically identical and GNS is a scaling voltage that defines the gain slope (the decibel change per voltage). The gain decreases with increasing V well matched, process and temperature dependent variations SET. are effectively cancelled. The VGA output is VSIG = GSET × RFIN = GO × RFIN exp(VSET/VGNS) (2) where RFIN is the ac voltage applied to the input terminals of the AD8363.
SUMMING VTGT V NODE ATG = 20 INHI V I SIG SQR ITGT VGA X2 X2 VTGT INLO GSET CLPF VSET CLPF CF VOUT (EXTERNAL) (INTERNAL) VPOS COMM TCM1 C TEMPERATURE COMPENSATION H CHPF AND BIAS TCM2/PWDN (INTERNAL) (EXTERNAL) TEMPERATURE CHPF TEMP (1.4V) SENSOR BAND GAP
076
VREF (2.3V)
68-
REFERENCE
073 Figure 33. Simplified Architecture Details Rev. B | Page 14 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE CHOICE OF RF INPUT PIN SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE MEASUREMENT MODE BASIC CONNECTIONS SYSTEM CALIBRATION AND ERROR CALCULATION OPERATION TO 125°C OUTPUT VOLTAGE SCALING OFFSET COMPENSATION, MINIMUM CLPF, AND MAXIMUM CHPF CAPACITANCE VALUES CHOOSING A VALUE FOR CLPF RF PULSE RESPONSE AND VTGT CONTROLLER MODE BASIC CONNECTIONS CONSTANT OUTPUT POWER OPERATION DESCRIPTION OF RF CHARACTERIZATION EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE