Data SheetADRV9008-1Parameter SymbolMinTypMaxUnitTestConditions/Comments Low Level −10 +10 μA Logic Outputs Output Voltage High Level VDD_ V INTERFACE × 0.8 Low Level VDD_ V INTERFACE × 0.2 Drive Capability 3 mA DIGITAL SPECIFICATIONS (CMOS): GPIO_3p3_x Logic Inputs Input Voltage High Level VDDA_ VDDA_3P3 V 3P3 × 0.8 Low Level 0 VDDA_ V 3P3 × 0.2 Input Current High Level −10 +10 μA Low Level −10 +10 μA Logic Outputs Output Voltage High Level VDDA_ V 3P3 × 0.8 Low Level VDDA_ V 3P3 × 0.2 Drive Capability 4 mA DIGITAL SPECIFICATIONS, LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) Logic Inputs (SYSREF_IN±, SYNCINx±) Input Voltage Range 825 1675 mV Each differential input in the pair Input Differential Voltage −100 +100 mV Threshold Receiver Differential 100 Ω Internal termination enabled Input Impedance SPI TIMING See the UG-1295 for more information SCLK Period tCP 20 ns SCLK Pulse Width tMP 10 ns CS Setup to First SCLK tSC 3 ns Rising Edge Last SCLK Falling Edge to CS tHC 0 ns Hold SDIO Data Input Setup to tS 2 ns SCLK SDIO Data Input Hold to tH 0 ns SCLK SCLK Rising Edge to Output tCO 3 8 ns Data Delay (3-Wire Mode or 4-Wire Mode) Bus Turnaround Time, Read tHZM tH tCO ns After Baseband Processor (BBP) Drives Last Address Bit Rev. 0 | Page 7 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide
