Datasheet AD9375 (Analog Devices) - 3

Data Sheet AD9375 FUNCTIONAL BLOCK DIAGRAM AD9375 RX1+ Rx1 DECIMATION, RX1– LPF Rx2 pFIR, AGC, DC OFFSET RX2+ ADC QEC, JESD204B TUNING, RX2– LPF RSSI, ADC OVERLOAD MICRO- CONTROLLER RX_EXTLO+ LO RF RX_EXTLO– GENERATOR SYNTHESIZER CONTROL EXTERNAL CTRL INT INTERFACE OPTION TX1+ Tx1 SPI SPI PORT TX1– LPF Tx2 TX2+ DAC pFIR, D TX2– LPF DC OFFSET, DP QEC, TUNNING, JESD204B DAC INTER- POLATION TX_EXTLO+ LO RF GPIO TX_EXTLO– GENERATOR SYNTHESIZER AUXADC EXTERNAL AUXDAC OPTION LO GENERATOR RF SYNTHESIZER CLOCK DEV_CLK_IN+, GENERATOR OBSERVATION DEV_CLK_IN– Rx ORX1+ ORX1– ORX2+ ORX2– SNIFFER SNRXA+ Rx LPF DECIMATION, SNRXA– pFIR, ADC AGC, SNRXB+ DC OFFSET, JESD204B SNRXB– LPF QEC, SNRXC+ TUNING, ADC RSSI, SNRXC–
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15657- Figure 1. Rev. 0 | Page 3 of 61 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence Digital Predistortion (DPD) JTAG Boundary Scan Outline Dimensions Ordering Guide