Datasheet AD9371 (Analog Devices) - 56

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AD9371 Data Sheet Table 8. Example Rx/Tx Interface Rates (Two Rx/Two Tx Channels, Maximum JESD Lane Rates) Tx/Tx Synthesis/ Tx Input Rx Output JESD204B Lane Rate JESD204B (No. Rx Bandwidth (MHz) Rate (MSPS) Rate (MSPS) (Mbps), Two Tx/Two Rx of Lanes) Tx/Rx Reference Clock Options (MHz)
100/250/100 307.2 153.6 6144 4/2 122.88, 153.6, 245.76, 307.2 75/200/100 245.76 122.88 4915.2 4/2 122.88, 245.76 20/100/40 122.88 61.44 2457.6 4/2 122.88, 245.76 20/100/20 122.88 30.72 2457.6 4/1 122.88, 245.76
TRANSMITTER TRANSMITTER QUADRATURE DIGITAL I/Q DAC HALF-BAND TRANSMITTER FIR HALF-BAND ERROR GAIN JESD204B FILTER 2 (INTERPOLATION
25
FILTER 1 CORRECTION
1
1, 2, 4)
1- 465 1 Figure 230. Example Tx Data Path Filter Implementation
DEC5 RECEIVER RECEIVER RECEIVER RFIR QEC DIGITAL DC ADC HALF-BAND HALF-BAND HALF-BAND JESD204B (DECIMATION CORRECTION GAIN CORRECTION FILTER 3 FILTER 2 FILTER 1 1, 2, 4) FILTER
126 14651- Figure 231. Data Rx Data Path Filter Implementation
POWER SUPPLY SEQUENCE Table 9. Dual-Function Boundary Scan Test Pins
The AD9371 requires a specific power-up sequence to avoid
Mnemonic JTAG Mnemonic Description
undesired power-up currents. The optimal power-on sequence GPIO_4 TRST Test access port reset starts the process by powering up the VDIG and the VDDA_1P3 GPIO_5 TDO Test data output (analog) supplies simultaneously. If they cannot power up GPIO_6 TDI Test data input simultaneously, the VDIG supply must power up first. The GPIO_7 TMS Test access port mode select VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies GPIO_18 TCK Test clock must then power up after the VDIG and VDDA_1P3 supplies. Note that the VDD_IF supply can power up at any time. It is
Table 10. JTAG Modes
also recommended to toggle the RESET signal after power has
Test Pin Level GPIO_0 to GPIO_3 Description
stabilized prior to configuration. Follow the reverse order of 0 XXXX1 Normal operation the power-up sequence to power-down. 1 1001 JTAG mode with LVDS JESD204B sync signals Note that VDDA_1P3 refers to all analog 1.3 V supplies 1 1011 JTAG mode with CMOS including the following: VDDA_BB, VDDA_CLKSYNTH, JESD204B sync signals VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, 1 VDDA_RXVCO, VDDA_RXTX, VDDA_TXSYNTH, X means don’t care. VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
JTAG BOUNDARY SCAN
The AD9371 provides support for a JTAG boundary scan. There are five dual-function pins associated with the JTAG interface. These pins, listed in Table 9, are used to access the on-chip test access port. To enable the JTAG functionality, set the GPIO_0 through GPIO_3 pins according to Table 10 depending on how the desired JESD204B sync pin (that is, SYNCINB0+, SYNCINB0−, SYNCINB1+, SYNCINB1−, SYNCBOUTB0+, or SYNCBOUTB0−) is configured in the software (LVDS or CMOS mode). Pull the TEST pin high to enable the JTAG mode. Rev. B | Page 56 of 57 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL External LO Inputs Serial Peripheral Interface (SPI) Interface GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence JTAG Boundary Scan Outline Dimensions Ordering Guide